Patents by Inventor Chih-Jen Chang
Chih-Jen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240126002Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.Type: ApplicationFiled: October 2, 2023Publication date: April 18, 2024Applicant: Coretronic CorporationInventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11923304Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a conductive interconnect disposed on a dielectric over a substrate. An interfacial layer is arranged along an upper surface of the conductive interconnect. A liner is arranged along a lower surface of the conductive interconnect. The liner and the interfacial layer surround the conductive interconnect. A middle layer is located over the interfacial layer and has a bottommost surface over the dielectric. A bottommost surface of the interfacial layer and the bottommost surface of the middle layer are both above a top of the conductive interconnect.Type: GrantFiled: November 28, 2022Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
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Patent number: 11687264Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.Type: GrantFiled: September 29, 2017Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Chih-Jen Chang, Brad Burres, Jose Niell, Dan Biederman, Robert Cone, Pat Wang, Kenneth Keels, Patrick Fleming
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Publication number: 20220197805Abstract: Examples described herein relate to at least one processor and circuitry, when operational, to: in connection with a request from a device to copy data to a destination memory address: based on a page fault, copy the data to a backup page and after determination of a virtual-to-physical address translation, copy the data from the backup page to a destination page identified by the physical address. In some examples, the copy the data to a backup page is based on a page fault and an indication that a target buffer for the data is at or above a threshold level of fullness. In some examples, copying the data to a backup page includes: receive the physical address of the backup page from the device and copy data from the device to the backup page based on identification of the backup page.Type: ApplicationFiled: September 20, 2021Publication date: June 23, 2022Inventors: Shaopeng HE, Anjali Singhai JAIN, Patrick MALONEY, Yadong LI, Chih-Jen CHANG, Kun TIAN, Yan ZHAO, Rajesh M. SANKARAN, Ashok RAJ
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Publication number: 20220182396Abstract: An example method for a device to handle a file in an antivirus action has been disclosed. The method includes in response to receiving a signal indicative of having detected malware associated with the file, resetting a first session with a first client device and storing metadata associated with the file in a cache. The method further includes after having received the signal and in response to receiving a second request for the file from the first client device to establish a second session, retrieving the metadata from the cache, maintaining the second session, identifying a first part of the file based on the retrieved metadata during the second session, and performing the antivirus action to the identified first part of the file during the second session.Type: ApplicationFiled: November 1, 2021Publication date: June 9, 2022Applicant: Lionic CorporationInventors: Chien-Ming CHEN, Ting-Chun HUANG, Chih-Jen CHANG
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Publication number: 20220116487Abstract: A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Naru Dames SUNDAR, Chih-Jen CHANG
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Publication number: 20220103530Abstract: Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.Type: ApplicationFiled: December 7, 2021Publication date: March 31, 2022Inventors: Daniel DALY, Anjali Singhai JAIN, Yadong LI, Stephen DOYLE, Naru Dames SUNDAR, Chih-Jen CHANG, Sailesh BISSESSUR, Andrew CUNNINGHAM, Edwin VERPLANKE, Patrick FLEMING
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Publication number: 20220014459Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicant: Intel CorporationInventors: Mrittika Ganguli, Anjali Jain, Reshma Lal, Edwin Verplanke, Priya Autee, Chih-Jen Chang, Abhirupa Layek, Nupur Jain
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Publication number: 20210288910Abstract: Examples described herein relate to a network interface device and in some examples, the network interface device includes an Ethernet interface, a host interface, circuitry to be configured to copy a packet payload from a host device through the host interface, form a packet based on the packet payload, and transmit the packet through the Ethernet interface, and circuitry to be configured to apply rate limiting and/or traffic shaping for packets received through the Ethernet interface based on hierarchical quality of service (H-QoS).Type: ApplicationFiled: May 27, 2021Publication date: September 16, 2021Inventors: Daniel DALY, Anjali Singhai JAIN, Chih-Jen CHANG, Edmund CHEN, Robert HATHAWAY, Naru Dames SUNDAR, Pawel SZYMANSKI, John MANGAN
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Patent number: 11108697Abstract: Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.Type: GrantFiled: March 30, 2018Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Chih-Jen Chang, Robert Southworth, Naru Dames Sundar, Yue Yang, Charles Michael Atkin, John Leshchuk
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Patent number: 11095571Abstract: IEEE 802.1Q and Enhanced Transmission Selection provide only eight different traffic classes that may be used to control bandwidth in a particular physical connection (or link). Instead of relying only on these eight traffic classes to manage bandwidth, the embodiments discussed herein disclose using an Enhanced Transmission Selection scheduler that permits a network device to set the bandwidth for an individual virtual LAN. Allocating bandwidth in a port based on a virtual LAN ID permits a network device to allocate bandwidth to, e.g., millions of unique virtual LANs. Thus, this technique may increase the granular control of the network fabric and its performance.Type: GrantFiled: November 2, 2017Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: William J. Armstrong, Claude Basso, Chih-Jen Chang, Mircea Gusat, Cyriel J. Minkenberg, Fredy D. Neeser, Kenneth M. Valk
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Patent number: 11050554Abstract: Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.Type: GrantFiled: December 30, 2017Date of Patent: June 29, 2021Assignee: Intel CorporationInventors: Naru Sundar, Chih-Jen Chang, Robert Southworth, Hsi-Cheng Chu
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Patent number: 10812402Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.Type: GrantFiled: December 28, 2018Date of Patent: October 20, 2020Assignee: Intel CorporationInventors: Robert Southworth, Ben-Zion Friedman, Robert Munoz, Sarig Livne, Chih-Jen Chang, Yue Yang, Partick Fleming
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Patent number: 10795200Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.Type: GrantFiled: January 22, 2019Date of Patent: October 6, 2020Assignee: INNOLUX CORPORATIONInventors: Chien-Chih Chen, Chia-Chun Yang, Chin-Cheng Kuo, Hsin-Tien Wu, Chih-Jen Chang
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Patent number: 10768841Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.Type: GrantFiled: September 30, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Linden Cornett, Chih-Jen Chang, Manasi Deval, Parthasarathy Sarangam, Naru D. Sundar, Padma Akkiraju, Alexander Nguyen
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Publication number: 20190207868Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.Type: ApplicationFiled: February 15, 2019Publication date: July 4, 2019Inventors: Chih-Jen CHANG, Daniel Christian BIEDERMAN, Matthew James WEBB, Wing CHEUNG, Jose NIELL, Robert HATHAWAY
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Publication number: 20190171060Abstract: A display device includes a display panel, a light shielding unit and a back plate. The display panel includes a first substrate, a second substrate and an upper polarizer. The first substrate is disposed corresponding to the second substrate. The upper polarizer is disposed on the second substrate. The light shielding unit is connected to the upper polarizer. The first substrate is disposed on the back plate.Type: ApplicationFiled: January 22, 2019Publication date: June 6, 2019Inventors: Chien-Chih CHEN, Chia-Chun YANG, Chin-Cheng KUO, Hsin-Tien WU, Chih-Jen CHANG
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Publication number: 20190140964Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Robert Southworth, Ben-Zion Friedman, Robert Munoz, Sarig Livne, Chih-Jen Chang, Yue Yang, Partick Fleming
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Patent number: 10234715Abstract: A display device includes a display panel, a light shielding unit, a supporting unit, and a backlight module. The display panel includes a first substrate and a first polarizer. The first substrate has a first surface, and the first surface has a first active area and a first non-active area. The first non-active area is disposed adjacent to the first active area, and the first polarizer is disposed on the first active area. The light shielding unit is disposed on the first non-active area and connected to the first polarizer. The supporting unit is disposed corresponding to the light shielding unit. The backlight module is disposed corresponding to the display panel and includes an optical film. The supporting unit is disposed between the light shielding unit and the optical film, and contacts the light shielding unit and the optical film.Type: GrantFiled: October 25, 2017Date of Patent: March 19, 2019Assignee: Innolux CorporationInventors: Chien-Chih Chen, Chia-Chun Yang, Chin-Cheng Kuo, Hsin-Tien Wu, Chih-Jen Chang