Patents by Inventor Chih-Jen Chang

Chih-Jen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10868353
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong
  • Patent number: 10867920
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Su-Jen Sung, Chih-Chiang Chang, Chia-Ho Chen
  • Patent number: 10841547
    Abstract: The present invention provides a method for fabricating small right angle prism mirrors, projecting system, and small right angle prism mirrors fabricated by a semiconductor process. The method comprises: coating a reflecting layer on a top surface of a glass substrate; forming an optical glue layer on a bottom surface of the glass substrate; utilizing a mold to form a 3D shape on the optical glue layer; exposing the optical glue layer having the 3D shape to solidify the optical glue layer having the 3D shape and combine the glass substrate having the reflecting layer and the optical glue layer having the 3D shape; removing the mold to form a small prism array; and dicing the small prism array to generate a plurality of small right angle prism mirrors.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: November 17, 2020
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Han-Yi Kuo, Yin-Dong Lu, Shi-Jen Wu, Chih-Sheng Chang, Teng-Te Huang
  • Patent number: 10840134
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-yi Ruan
  • Publication number: 20200357922
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20200350777
    Abstract: A controller for managing a battery pack includes: a detection terminal, for transmitting an enable signal when values of battery parameters for the battery pack satisfy a sleep condition, where the enable signal enables the detection circuit to detect whether the battery pack is connected to a load and whether the battery pack is connected to the charger; and a receiving terminal, for receiving a detection result transmitted by the detection circuit. The detection result indicates whether the battery pack is connected to at least one of the load and charger. The controller controls the battery pack to enter a sleep mode of the sleep modes based on the detection result. The controller also includes a control terminal, for transmitting a control signal to control an on/off state of a charging switch and/or a discharging switch. The control signal is generated by the controller based on the detection result.
    Type: Application
    Filed: February 24, 2020
    Publication date: November 5, 2020
    Inventors: Yingguo ZHANG, Guoyan QIAO, Fu-Jen Hsieh, Chia-Ming CHANG, Chih-Chung CHOU, Hua-Yi WANG
  • Patent number: 10812402
    Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Robert Southworth, Ben-Zion Friedman, Robert Munoz, Sarig Livne, Chih-Jen Chang, Yue Yang, Partick Fleming
  • Patent number: 10768841
    Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Linden Cornett, Chih-Jen Chang, Manasi Deval, Parthasarathy Sarangam, Naru D. Sundar, Padma Akkiraju, Alexander Nguyen
  • Publication number: 20200271873
    Abstract: In an embodiment, a package structure including an electro-optical circuit board, a fanout package disposed over the electro-optical circuit board is provided. The electro-optical circuit board includes an optical waveguide. The fanout package includes a first optical input/output portion, a second optical input/output portion and a plurality of electrical input/output terminals electrically connected to the electro-optical circuit board. The first optical input/output portion is optically coupled to the second optical input/output portion through the optical waveguide of the electro-optical circuit board.
    Type: Application
    Filed: February 21, 2019
    Publication date: August 27, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Lun Chang, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hsuan-Ting Kuo, Chia-Shen Cheng, Chih-Chiang Tsao
  • Patent number: 10742124
    Abstract: A power converter using an active-clamp flyback topology has a low-side switch, a high-side switch and a control circuit. The low-side switch connects a primary winding of a transformer to an input ground line, and the high-side switch is connected in series with a capacitor to form an active-clamp circuit connected in parallel with the primary winding. The control circuit provides high-side and low-side signals to the high-side and the low-side switches respectively, in response to a current-sense signal and a compensation signal. The control circuit is configured to operate the power converter in one of operation modes including a complementary mode and a non-complementary mode. When operated in the complementary mode, the high-side signal and the low-side signal are substantially complementary to each other, and the control circuit exits the complementary mode in response to the current-sense signal to enter the non-complementary mode.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 11, 2020
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Yao Tsung Chen, Chih Chi Chang, Meng Jen Tsai
  • Publication number: 20200251449
    Abstract: A semiconductor device package includes a substrate, a connection structure, a first package body and a first electronic component. The substrate has a first surface and a second surface opposite to the first surface. The connection structure is disposed on the firs surface of the substrate. The first package body is disposed on the first surface of the substrate. The first package body covers the connection structure and exposes a portion of the connection structure. The first electronic component is disposed on the first package body and in contact with the portion of the connection structure exposed from the first package body.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shang-Ruei Wu, Chien-Yuan Tseng, Meng-Jen Wang, Chen-Tsung Chang, Chih-Fang Wang, Cheng-Han Li, Chien-Hao Chen, An-Chi Tsao, Per-Ju Chao
  • Patent number: 10723841
    Abstract: A method for preparing a compound and a method for preparing a polymer employing the same are provided. The method for preparing a compound includes reacting a compound having a structure represented by Formula (I) with a compound having a structure represented by Formula (III) in the presence of a compound having a structure represented by Formula (II) to obtain a compound having a structure represented by Formula (IV) wherein Ar1 is substituted or unsubstituted aryl group; X is —O—, —S—, or —NH—; R1 is independently hydrogen or C1-6 alkyl group; R2 is hydroxyl group, C1-6 alkyl group, phenyl group, or tolyl group; and R3 is independently C1-6 alkyl group, C5-8 cycloalkyl group, or C2-6 alkoxyalkyl group.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH
    Inventors: Po-Hsien Ho, Chih-Hsiang Lin, Feng-Jen Tsai, Cheng-Hsing Fan, Yih-Her Chang, Hsin-Ching Kao, Chien-Ming Chen
  • Patent number: 10727350
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 10707282
    Abstract: A display may have organic light-emitting diode pixels formed from thin-film circuitry. An organic layer including planarization layers and a pixel definition layer may overlap the thin-film circuitry. Thin-film encapsulation may overlap the organic layer. The thin-film encapsulation may be formed from an organic dielectric layer interposed between two layers of inorganic dielectric material. A strip of peripheral crack-stopper structures may run along an edge of the display and may surround the array of pixels. The crack-stopper structures may include parallel inorganic lines formed from a first inorganic layer such as an inorganic layer of the thin-film circuitry. A strip of the organic layer may overlap the parallel inorganic lines. The crack-stopper structures may have parallel tapered polymer lines. The polymer lines may be overlapped by a second inorganic dielectric layer formed from the inorganic material of the thin-film encapsulation layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: July 7, 2020
    Assignee: Apple Inc.
    Inventors: Chih Jen Yang, Prashant Mandlik, Chia-Hao Chang, Chien-Chung Wang, Te-Hua Teng, Yu Cheng Chen
  • Patent number: 10677841
    Abstract: A composite product testing system including a main management system, a test equipment and a burn-in apparatus is disclosed. The test equipment and the burn-in apparatus are both arranged in a burn-in chamber of the testing system. First, multiple tested products are respectively inserted in multiple gauges of the burn-in chamber, and a burn-in procedure is activated for providing an aging environment. The main management system controls one of the gauges to connect with the test equipment for the test equipment to perform testing on the tested product upon the connected gauge. After the testing is completed, the main management system then controls the gauge to disconnect from the test equipment and re-connect with the burn-in apparatus, so as to monitor the tested product upon the gauge during the burn-in procedure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 9, 2020
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chien-Chung Chang, Hung-Pin Yu, Yu-Jen Chen, Wen-Jen Lo, Chih-Yen Liu
  • Patent number: 10666153
    Abstract: A control method for a power convert is disclosed. The power convert uses an active-clamp flyback topology and has low-side and high-side switches. The low-side switch is switched to generate consecutive switching cycles including a modified flyback cycle and a normal flyback cycle. Each of the consecutive switching cycles is not less than a blanking time generated in response to a load of the power converter. The high-side switch is constantly turned OFF during the normal flyback cycle. The high-side switch is turned ON after the blanking time during the modified flyback cycle to perform zero-voltage switching for the low-side switch.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 26, 2020
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Yao Tsung Chen, Chih Chi Chang, Meng Jen Tsai
  • Publication number: 20200161275
    Abstract: A package includes a die on a surface of a package component. The package also includes a first die stack on the surface of the package component. The package further includes a first thermal interface material (TIM) having a first thermal conductivity and disposed on the first die stack. In addition, the package includes a second thermal interface material (TIM) having a second thermal conductivity and disposed on the die. The first thermal conductivity of the first TIM is different from the second thermal conductivity of the second TIM.
    Type: Application
    Filed: November 11, 2019
    Publication date: May 21, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Pu-Sheng LEE, Fu-Jen LI, Hsien-Liang MENG
  • Publication number: 20200152616
    Abstract: A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases.
    Type: Application
    Filed: January 12, 2020
    Publication date: May 14, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-Shuan Chung
  • Publication number: 20200106368
    Abstract: A control method for a power convert is disclosed. The power convert uses an active-clamp flyback topology and has low-side and high-side switches. The low-side switch is switched to generate consecutive switching cycles including a modified flyback cycle and a normal flyback cycle. Each of the consecutive switching cycles is not less than a blanking time generated in response to a load of the power converter. The high-side switch is constantly turned OFF during the normal flyback cycle. The high-side switch is turned ON after the blanking time during the modified flyback cycle to perform zero-voltage switching for the low-side switch.
    Type: Application
    Filed: August 23, 2019
    Publication date: April 2, 2020
    Inventors: Yao Tsung CHEN, Chih Chi CHANG, Meng Jen TSAI
  • Publication number: 20200106156
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a chip package, an antenna pattern, and an insulating layer. The chip package includes a semiconductor die and an insulating encapsulation enclosing the semiconductor die. The antenna pattern is electrically coupled to the chip package, where a material of the antenna pattern comprises a conductive powder having fused metal particles. The insulating layer disposed between the chip package and the antenna pattern, where the antenna pattern includes a first surface in contact with the insulating layer, and a second surface opposite to the first surface, and a surface roughness of the second surface is greater than a surface roughness of the first surface.
    Type: Application
    Filed: April 18, 2019
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Lin Lu, Hsiu-Jen Lin, Hsuan-Ting Kuo, Kai-Chiang Wu, Ming-Che Ho, Wei-Yu Chen, Yu-Peng Tsai, Chia-Lun Chang, Chia-Shen Cheng, Chih-Chiang Tsao, Tzu-Chun Tang, Ching-Hua Hsieh, Tuan-Yu Hung, Cheng-Shiuan Wong