Patents by Inventor Chih-Jen Chang
Chih-Jen Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120230340Abstract: A network node that forwards traffic of a converged network received from a source end node receives a second message addressed to the network node, but intended for the source end node. The second message includes at least a portion of a first message originated by the source end node and previously forwarded by the network node. The network node extracts from the first message a source identifier of the source end node in a first communication protocol and determines by reference to a data structure a destination address of the second message in a second communication protocol. The network node modifies the second message to include the destination address and forwards the second message toward the source end node in accordance with the destination address.Type: ApplicationFiled: April 26, 2012Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: WILLIAM J. ARMSTRONG, CLAUDE BASSO, CHIH-JEN CHANG, JOSEP CORS, DANIEL G. EISENHAUER, HENRY J. MAY, CHRISTOPH RAISCH, RENATO J. RECIO, COLIN B. VERRILLI, CHETAN S. YALIWAL
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Publication number: 20120204002Abstract: A mechanism is provided for sharing a communication used by a parser (parser path) in a network adapter of a network processor for sending requests for a process to be executed by an external coprocessor. The parser path is shared by processors of the network processor (software path) to send requests to the external processor. The mechanism uses for the software path a request mailbox comprising a control address and a data field accessed by MMIO for sending two types of messages, one message type to read or write resources and one message type to trigger an external process in the coprocessor and a response mailbox for receiving response from the external coprocessor comprising a data field and a flag field. The other processors of the network poll the flag until set and get the coprocessor result in the data field.Type: ApplicationFiled: February 3, 2012Publication date: August 9, 2012Applicant: Internaitonal Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Publication number: 20120204190Abstract: A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.Type: ApplicationFiled: February 3, 2012Publication date: August 9, 2012Applicant: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Publication number: 20120192190Abstract: A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice J. Verplanken, Colin B. Verrilli
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Patent number: 8225188Abstract: Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.Type: GrantFiled: August 29, 2008Date of Patent: July 17, 2012Assignee: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Chih-Jen Chang, Philippe Damon, Ronald Edward Fuhs, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli, Scott Michael Willenborg
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Publication number: 20120159132Abstract: Mechanisms are provided for a network processor comprising a parser, the parser being operable to work in normal operation mode or in repeat operation mode, the parser in normal operation mode loading and executing at least one rule in a first and a second working cycle respectively, the parser in repeat operation mode being operable to repeatedly execute a repeat-instruction, the execution of each repeat corresponding to one working cycle.Type: ApplicationFiled: July 15, 2011Publication date: June 21, 2012Applicant: International Business Machines CorporationInventors: Francois Abel, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Fabrice J. Verplanken
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Publication number: 20120059097Abstract: In an embodiment, a starch-based thermoplastic composite is provided. The starch-based thermoplastic composite includes thermoplastic starch (TPS), polycarbonate (PC) and acrylonitrile butadiene styrene (ABS), wherein the polycarbonate has a weight ratio of 15-60% in the starch-based thermoplastic composite. The starch-based thermoplastic composite further includes an impact modifier and a compatibilizer.Type: ApplicationFiled: March 4, 2011Publication date: March 8, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Sheng-Ju Liao, Chien-Ming Chen, Chih-Jen Chang, Yao-Chu Chung, Cheng-Feng Liao, Hsieh-Yung Chang
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Patent number: 8047668Abstract: A backlight module includes at least one light source, a lamp cover and a circuit board. The lamp cover has a containing portion and at least one projection. The containing portion is arranged for containing the light source. The projection is located at an outer side of the containing portion on which the circuit board is placed so that at least one fixing portion of the circuit board is in contact with the projection for constraining movements of the circuit board relative to the lamp cover.Type: GrantFiled: February 25, 2009Date of Patent: November 1, 2011Assignee: Chimei Innolux CorporationInventors: Chih-Jen Chang, Shun-Nan Chang
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Patent number: 7995472Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.Type: GrantFiled: January 6, 2009Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Jean L. Calvignac, Chih-jen Chang, Joseph F. Logan, Fabrice J. Verplanken, Daniel Wind
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Publication number: 20110158254Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, a source is selected in a manner that maintains fairness in the selection process. A corresponding sink is selected for the selected source based on processing efficiency. If, due to assignment constraints, no sink is available for the selected source, the selected source is retained for selection in the next scheduling period, to maintain fairness. In this case, to optimize efficiency, a most efficient currently available sink is identified and a source for providing work to that sink is selected.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claude Basso, Jean L. Calvignac, Chih-Jen Chang, Hubertus Franke, Colin Beaton Verrilli
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Publication number: 20110158249Abstract: An assignment constraint matrix method and apparatus used in assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. The assignment constraint matrix is implemented as a plurality of qualifier matrixes adapted to operate simultaneously in parallel. Each of the plurality of qualifier matrixes is adapted to determine sources in a subset of supported sources that are qualified to provide work to a set of sinks based on assignment constraints. The determination of qualified sources may be based sink availability information that may be provided for a set of sinks on a single chip or distributed on multiple chips.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claude Basso, Jean L. Calvignac, Chih-Jen Chang, Hubertus Franke, Fabrice J. Verplanken, Colin B. Verrilli
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Publication number: 20110158250Abstract: A method and apparatus for assigning work, such as data packets, from a plurality of sources, such as data queues in a network processing device, to a plurality of sinks, such as processor threads in the network processing device. In a given processing period, sinks that are available to receive work are identified and sources qualified to send work to the available sinks are determined taking into account any assignment constraints. A single source is selected from an overlap of the qualified sources and sources having work available. This selection may be made using a hierarchical source scheduler for processing subsets of supported sources simultaneously in parallel. A sink to which work from the selected source may be assigned is selected from available sinks qualified to receive work from the selected source.Type: ApplicationFiled: December 30, 2009Publication date: June 30, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Claude Basso, Jean L. Calvignac, Chih-Jen Chang, Hubertus Franke, Terry L. Nelms, II, Fabrice Jean Verplanken
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Patent number: 7953951Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.Type: GrantFiled: May 21, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Chih-jen Chang, Gordon Taylor Davis, Harm Peter Hofstee, Fabrice Jean Verplanken, Colin Beaton Verrilli
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Patent number: 7929438Abstract: A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.Type: GrantFiled: July 18, 2008Date of Patent: April 19, 2011Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Gordon T. Davis, Fabrice J. Verplanken
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Patent number: 7930742Abstract: Methods and systems for processing multiple levels of data in system security approaches are disclosed. In one embodiment, a first set and a second set of resources are selected to iteratively and independently reverse multiple levels of format conversions on the payload portions of a data unit from a first file and a data unit from a second file, respectively. The first file and the second file are associated with a first transport connection and a second transport connection, respectively. Upon completion of the aforementioned reversal operations, the payload portions of a first reversed data unit and a second reversed data unit, which correspond to the data unit of the first file and the data unit of the second file, respectively, are inspected for suspicious patterns prior to any aggregation of the data units of the first file or the second file.Type: GrantFiled: June 5, 2006Date of Patent: April 19, 2011Assignee: Lionic CorporationInventors: Chih-Jen Chang, Shi-Ming Zhao, Shih-Wei Chien
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Patent number: 7912988Abstract: A mechanism for offloading the management of receive queues in a split (e.g. split socket, split iSCSI, split DAFS) stack environment, including efficient queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates receive work queues and completion queues that are utilized by an Internet Protocol Suite Offload Engine (IPSOE) and the ULP to transfer information and carry out send operations. As consumers initiate receive operations, receive work queue entries (RWQEs) are created by the ULP and written to the receive work queue (RWQ). The ISPOE is notified of a new entry to the RWQ and it subsequently reads this entry that contains pointers to the data that is to be received. After the data is received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). After the CQE is written, the ULP subsequently processes the entry and removes it from the CQE, freeing up a space in both the RWQ and CQ.Type: GrantFiled: July 14, 2006Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: William Todd Boyd, Jean L. Calvignac, Chih-Jen Chang, Douglas J. Joseph, Renato John Recio
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Patent number: 7913034Abstract: Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.Type: GrantFiled: August 1, 2007Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Jean L. Calvignac, Chih-jen Chang, Gordon T. Davis, Fabrice J. Verplanken
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Patent number: 7903687Abstract: A method for receiving packets in a computer network are disclosed. The method include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.Type: GrantFiled: April 1, 2005Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Chih-jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli
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Patent number: 7881332Abstract: A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.Type: GrantFiled: April 1, 2005Date of Patent: February 1, 2011Assignee: International Business Machines CorporationInventors: Claude Basso, Jean Louis Calvignac, Chih-Jen Chang, Philippe Damon, Natarajan Vaidhyanathan, Fabrice Jean Verplanken, Colin Beaton Verrilli
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Patent number: 7818362Abstract: A mechanism for offloading the management of send queues in a split socket stack environment, including efficient split socket queue flow control and TCP/IP retransmission support. An Upper Layer Protocol (ULP) creates send work queue entries (SWQEs) for writing to the send work queue (SWQ). The Internet Protocol Suite Offload Engine (IPSOE) is notified of a new entry to the SWQ and it subsequently reads this entry that contains pointers to the data that is to be transmitted. After the data is transmitted and acknowledgments are received, the IPSOE creates a completion queue entry (CQE) that is written into the completion queue (CQ). The flow control between the ULP and the IPSOE is credit based. The passing of CQ credits is the only explicit mechanism required to manage flow control of both the SWQ and the CQ between the ULP and the IPSOE.Type: GrantFiled: May 5, 2006Date of Patent: October 19, 2010Assignee: International Business Machines CorporationInventors: William Todd Boyd, Jean L. Calvignac, Chih-Jen Chang, Douglas J. Joseph, Renato John Recio