Abstract: A process of forming silicon-based nanowires heats high-surface-oxygen-content silicon powders to initiate vapor-solid reaction to form nanowires. The reaction gas is charged to react with the Si powders to form the silicon-based nanowires such as silicon nanowires or SiC nanowires. With control of the reaction gas, the components of the nanowires can be exactly controlled without the addition of metallic catalysts. Thereby, the nanowires can be made with reduced cost.

Abstract: The present invention relates to a method for generating non-human mammalian chimeric embryo. The method involves coculturing denuded non-human mammalian embryos with cells in an Eppendorf micro test tube. The chimeric embryo obtained is then transferred into a non-human recipient mammal so as to develop into a non-human chimeric fetus, non-human chimeric mammal, an embryonic stem cell-derived fetus or an embryonic stem cell-derived mammal.

Abstract: An apparatus and method of testing an integrated circuit by downloading a sequence of randomly weighted bits into a scan chain in which each bit has a distinctly determined weight generated in real-time by a weight generator. The weight generator has a switch controlled by a stored bit particular for each bit of the randomly weighted bits that determines the weight of the bit. The control signal is stored in a memory that is downloaded into the switch in synchronization with the generation of the bit. Preferably, the memory is on-die, and furthermore is a part of the integrated circuit.

Abstract: Improved apparatus and methods for performing programmable built-in self-testing (PBIST) of memory serve to capture failure information while minimizing the silicon area used for implementation. Rather than saving all data subsequent to the first detection of a memory failure, on-chip storage elements save command, address, and program counter values corresponding to the instruction generating the first memory failure as well as to a number of subsequent instructions, but only a single memory block of data values is saved. The total silicon area of the elements that store the command, address, program counter, and data values is significantly less than that required to save all data corresponding to the first and subsequent faulty read operations. Methods of operation, as well as application of the apparatus to an electronic assembly, an electronic system, and a data processing system, are also described.

Abstract: An apparatus and method of testing an integrated circuit by downloading a sequence of randomly weighted bits into a scan chain in which each bit has a distinctly determined weight generated in real-time by a weight generator. The weight generator has a switch controlled by a stored bit particular for each bit of the randomly weighted bits that determines the weight of the bit. The control signal is stored in a memory that is downloaded into the switch in synchronization with the generation of the bit. Preferably, the memory is on-die, and furthermore is a part of the integrated circuit.

Abstract: A test point selection method for scan-based built-in self-test (BIST). The method calculates a hybrid cost reduction (HCR) value as an estimated value of the corresponding actual cost reduction for all nodes in a circuit under test. A test point is then selected having a largest HCR. This iterative process continues until the fault coverage of the circuit under test reaches a desired value or the number of test points selected is equal to a maximum number of test points. In an alternative embodiment, the cost reduction factor is calculated for all nodes in the circuit under test, the HCR is calculated for only a selected set of candidates, and the candidate having the largest HCR is selected as the test point. The test point selection method achieves higher fault coverage results and reduces computational processing relative to conventional selection methods.

Abstract: Test points (20, 24) placed at selected nodes (16) within a circuit (10) based on a cost function that accounts for (a) the global improvement in testability and (b) the penalty in circuit performance associated with propagation delays attributable to such test points. By accounting for both the global impact on testability and circuit performance degradation, the cost function maximizes fault coverage while achieving nearly minimal impairment of circuit performance.

Abstract: A bag assembly includes a bag body and a valve unit. The bag body confines a receiving space and is formed with a vent hole. The valve unit is provided in the vent hole and includes an upper sheet and a lower sheet which are heat-sealed to the bag body and which cooperatively confine an air passage that is communicated with the receiving space. The upper and lower sheets of the valve unit have opposing inner surfaces which are electrostatically charged such that the upper and lower sheets normally adhere to each other via an electrostatic attraction at the inner surfaces thereof, thereby closing the air passage of the valve unit.

Abstract: The testability of a near-acyclic circuit (14) can be enhanced by the addition of one or more control points (36) and observation points (34) to allow for increased observability and controllability of selected nodes (28). The control points (36) and/or test points (34) are added by first computing the controllability, observability and fault detection probability at each node. A fault is then selected. If either the controllability or observability for such fault is not inside a prescribed value range, and the fault detection probability is below a prescribed value, then either a control point (36) and/or a observation point (34) may be added.

Abstract: Testing of an integrated circuit (10), configured of a plurality of flip-flops (14.sub.1 -14.sub.n), at least a portion of which are arranged in a scan chain (16.sub.1 -16.sub.k), is carried out by replacing each self-looping, non-scan chain flip-flop (14.sub.6) with an initializable non-scan flip-flop (64). The integrated circuit (10), including each initializable flip-flop (64) therein, is then initialized prior to placing the integrated circuit in a non-operational mode. During the non-operational mode, a first test vector is shifted through the scan chain flip-flops, causing each to shift out a bit previously latched therein. The integrated circuit (10) is then returned to an operational mode, after which time, a second test vector is applied to its inputs, causing a response to appear at its outputs, and also causing a bit to be shifted into each scan chain flip-flop. The response of the integrated circuit is compacted with the bits shifted from the scan chain flip-flops.