Abstract: A flexible flat cable includes an upper bonding adhesive layer and a lower bonding adhesive layer bonded together, a plurality of bare wires being sandwiched, an upper metal shielding layer located on an upper side of the upper bonding adhesive layer and adhesively attached to the upper bonding adhesive layer, and a lower metal shielding layer located on a lower side of the lower bonding adhesive layer and adhesively attached to the lower side of the lower bonding adhesive layer.

Abstract: A connector assembly includes an inverted U-shaped case body which includes an upper cover body and two lateral bodies, an isolation insert plate, a first flexible cable, a second flexible cable, an upper insulating holding member, and a lower insulating holding member. Each of the two lateral bodies has at least one buckle hole, and two inner sides of the two lateral bodies respectively have a vertical concave portion. The isolation insert plate includes upper and lower surfaces, and each of two sides of a rear end of the isolation insert plate has a vertical engagement portion to be engaged with the concave portion.

Abstract: An inductor assembly includes a first magnetic core, a second magnetic core, a winding and a bonding material layer. The second magnetic core includes a channel. The winding is disposed within the channel. The bonding material layer is disposed between the first magnetic core and the second magnetic core and includes a first bonding material and a second bonding material. A magnetic permeability of the first bonding material is greater than a magnetic permeability of the second bonding material. The first bonding material and the second bonding material are disposed on the second magnetic core. A surface of the first bonding material faced to the first magnetic core and a surface of the second bonding material faced to the first magnetic core are coplanar with each other.

Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Abstract: A semiconductor device includes a substrate, a doped ring, a plurality of contacts, and a plurality of conductive lines. The substrate includes a first region and a second region surrounding the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The doped ring includes a first doped region and a plurality of second doped regions. The first doped region is located in the substrate in the second region and surrounds the first region. The first doped region has an opening. The second doped regions are separated from each other and located in the substrate of the opening. The contacts are electrically connected to the second doped regions. The conductive lines are connected to the contacts and a plurality of conductive layers in the first region.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: Provided is a flexible flat cable with no secondary processing adhesives. The flexible flat cable with no secondary processing adhesives includes a plurality of parallel arranged conductors, two insulation layers and two shielding layers. The two insulation layers have respective inner surfaces oppositely positioned to be adhered to sandwich the parallel arranged conductors. The two shielding layers are respectively adhered on respective outer surfaces of the two insulation layers. At least one of the inner surfaces or at least one of the outer surfaces of the two insulation layers is modified to have a modified surface layer possessing adhesibility.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A flexible flat cable includes an upper bonding adhesive layer and a lower bonding adhesive layer bonded together, a plurality of bare wires being sandwiched, an upper metal shielding layer located on an upper side of the upper bonding adhesive layer and adhesively attached to the upper bonding adhesive layer, and a lower metal shielding layer located on a lower side of the lower bonding adhesive layer and adhesively attached to the lower side of the lower bonding adhesive layer. The flexible flat cable does not need to be provided with an insulating material layer. It is small in size and simplified in structure. It not only can meet requirements of industries for characteristic impedance and insertion loss, but also can greatly reduce the cost, which in turn better satisfies the important issue of cost considerations of the industries.

Abstract: A connector assembly includes a connector and a flat cable. The connector includes a first terminal, a second terminal, a first body, a second body, a metal plate, a third body, and a shell. The first and second terminals electrically connect a first side and a second side of the flat cable respectively and are respectively contained in a first capacity slot and a first through-hole of the first body and in a second capacity slot and a second through-hole of the second body. The first and second bodies clamp the metal plate. The third body partly winds and fixes the first body and the second body, and protects a terminal conductive contact part of the flat cable connected by the first and second terminals to form the connector. The flat cable connects to the connector directly. There is no need for a fixed rigid printed circuit board.

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.

Abstract: An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

Abstract: Embodiments of the present disclosure are directed to a flexible flat cable for improving high-frequency transmission, which has a multi-layer structure. The flexible flat cable includes an upper plastic film layer, an upper adhesive film layer, a plurality of wires arranged in parallel, a lower adhesive film layer, and a lower plastic film layer in turn from top to bottom. At least two adjacent wires have a dielectric space, which is capable of reducing conductor loss, thereby reducing the attenuation of the signal and improving the signal integrity.

Abstract: Embodiments of the present disclosure are directed to a flexible flat cable. Two insulating material layers are sandwiched with a plurality of conductors therebetween by two adhesive layers, and a metal shielding layer is attached to an outer side of the two insulating material layers by a laminated adhesive layer. The conductors are bare conductors, and the laminated adhesive layer is a laminated adhesive layer with bubbles. The flexible flat cable is small in size, which not only meets the requirements of characteristic impedance and insertion loss in industry, but also significantly reduces the cost compared with the conventional flexible flat cable made of traditional electronic round wires.

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.