Patents by Inventor Chih-Jung Chen

Chih-Jung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381532
    Abstract: A semiconductor device includes a fin projecting upwardly from a substrate; a gate stack engaging the fin; a gate spacer on a sidewall of the gate stack and in contact with the gate stack; and a dielectric layer on the sidewall of the gate stack and in contact with the gate stack, the dielectric layer being vertically between the fin and the gate spacer, wherein the dielectric layer has a thickness small than the gate spacer.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung Jung Chang
  • Patent number: 10854742
    Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr-Jung Lin, Chih-Han Lin, Jin-Aun Ng, Ming-Ching Chang, Chao-Cheng Chen
  • Patent number: 10854504
    Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang
  • Publication number: 20200373401
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Publication number: 20200343135
    Abstract: A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 29, 2020
    Inventors: Chun-Hsien Huang, I-Li Chen, Pin-Wen Chen, Yuan-Chen Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Publication number: 20200321196
    Abstract: A dry etching apparatus includes a process chamber, a stage, a gas supply device and a plasma generating device. The stage is in the process chamber and is configured to support a wafer, wherein the wafer has a center region and a periphery region surrounding the center region. The gas supply device is configured to supply a first flow of an etching gas to the center region and supply a second flow of the etching gas to the periphery region. The plasma generating device is configured to generate plasma from the etching gas.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin CHEN, Tung-Wen CHENG, Che-Cheng CHANG, Jr-Jung LIN, Chih-Han LIN
  • Patent number: 10794400
    Abstract: A fan includes a rotating unit and a housing unit. The rotating unit includes a base and a fan body that is rotatably mounted to the base. The housing unit includes an outer ring that surrounds and is connected to the base, a plurality of connecting members that are mounted to an outer peripheral surface of the outer ring and that are spaced apart from each other, and a base member that surrounds the rotating unit and the outer ring and that is connected to the connecting members. The base member has a plurality of receiving holes, and each of the connecting members is made of a shock-absorbing material, and is fixed in a respective one of the receiving holes.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: October 6, 2020
    Assignee: YEN SUN TECHNOLOGY CORP.
    Inventors: Chien-Jung Chen, Hsin-Hsien Wu, Chih-Tsung Hsu
  • Publication number: 20200303211
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Application
    Filed: June 4, 2020
    Publication date: September 24, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: 10781265
    Abstract: A humanized anti-Globo H antibody, or an scFv or Fab fragment thereof, comprising a heavy-chain variable domain having three complementary regions consisting of HCDR1, HCDR2, and HCDR3 and a light-chain variable domain having three complementary regions consisting of LCDR1, LCDR2, and LCDR3, wherein the sequence of HCDR1 is GYISSDQILN (SEQ ID NO:4), the sequence of HCDR2 is RIYPVTGVTQYXHKFVG (SEQ ID NO:5, wherein X is any amino acid), and the sequence of HCDR3 is GETFDS (SEQ ID NO:6), wherein the sequence of LCDR1 is KSNQNLLX?SGNRRYZLV (SEQ ID NO:7, wherein X? is F, Y, or W, and Z is C, G, S or T), the sequence of LCDR2 is WASDRSF (SEQ ID NO:8), and the sequence of LCDR3 is QQHLDIPYT (SEQ ID NO:9).
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 22, 2020
    Assignee: Development Center for Biotechnology
    Inventors: Chia-Cheng Wu, Szu-Liang Lai, Yu-Jung Chen, Chih-Yung Hu, Tzu-Yin Lin
  • Publication number: 20200295160
    Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.
    Type: Application
    Filed: April 9, 2019
    Publication date: September 17, 2020
    Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
  • Publication number: 20200295051
    Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung-Jung Chang
  • Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Publication number: 20200266340
    Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Patent number: 10750644
    Abstract: A server device is provided with a fan module that includes a removable or reconfigurable partition for different size fan units based on system requirements. The chassis can include a plurality of sleds and a fan module. The fan module includes a removable partition that can be configured to house a plurality of fan units.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: August 18, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chao-Jung Chen, Chih-Wei Lin, Ming-Lun Ku
  • Patent number: 10749014
    Abstract: A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation structure and engaging the fin; and a gate spacer on a sidewall of the gate stack and in physical contact with the gate stack. The semiconductor device further includes a first dielectric layer vertically between the fin and the gate spacer. The semiconductor device further includes a second dielectric layer vertically between the first dielectric layer and the gate spacer, wherein the first and second dielectric layers include different materials, and wherein the second dielectric layer is in physical contact with the gate spacer and the first dielectric layer.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Che-Cheng Chang, Jr-Jung Lin, Shih-Hao Chen, Chih-Han Lin, Mu-Tsang Lin, Yung-Jung Chang
  • Patent number: 10736964
    Abstract: An immunomagnetic nanocapsule includes a core, a shell and an outer layer. The shell is formed by a complex, and the complex is fabricated by a combination of fucoidan, oxidized dextran, and a plurality of superparamagnetic iron oxide nanoparticles via a hydrophobic interaction. The core is encapsulated in the shell. The outer layer includes at least one antibody immobilized to outside of the shell to form the outer layer, wherein the antibody is an immune checkpoint inhibitor and/or a T cell expansion antibody.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 11, 2020
    Assignee: China Medical University
    Inventors: Woei-Cherng Shyu, San-Yuan Chen, Chih-Sheng Chiang, Chia-Hung Hsieh, Yu-Jung Lin, Chang-Hai Tsai
  • Publication number: 20200237938
    Abstract: The present invention provides a radioactive labeling method for neuropeptide Y (NPY) compound and a mammalian diagnostic radioactive targeting medicine with NPY peptide being modified at position 27th to 36th, and after binding with the chelating agent and labeling the radiation nucleus 66Ga, 67Ga, 68Ga, 177Lu or 111In to provide a radioactive targeting medicine for multi-type breast cancer diagnosis and treatment.
    Type: Application
    Filed: December 11, 2018
    Publication date: July 30, 2020
    Inventors: Ming-Hsin Li, Su-Jung Chen, Ming-Wei Chen, Yuan-Ruei Huang, Shih-Ying Lee, Chun-Fang Feng, Sheng-Nan Lo, Chih-Hsien Chang
  • Patent number: 10707094
    Abstract: A semiconductor package has a first redistribution layer, a first die, a second redistribution layer, and a surface coating layer. The first die is encapsulated within a molding material and disposed on and electrically connected to the first redistribution layer. The second redistribution layer is disposed on the molding material, on the first die, and electrically connected to the first die. The second redistribution layer has a topmost metallization layer having at least one contact pad, and the at least one contact pad includes a concave portion. The surface coating layer covers a portion of the topmost metallization layer and exposes the concave portion of the at least one contact pad. A manufacturing process is also provided.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Feng Chen, Chih-Hua Chen, Chen-Hua Yu, Chung-Shi Liu, Hung-Jui Kuo, Hui-Jung Tsai, Hao-Yi Tsai
  • Patent number: RE48135
    Abstract: A server system includes a rack, a power supply module, a switch, and a plurality of servers. The rack can be divided into a plurality of rack units. The rack units are parallel to each other and vertically arranged. The power supply module and the switch are disposed in close proximity to each other in at least one of the rack units. The power supply is adjacent to the rear side of the rack. The switch is adjacent to the front side of the rack. Each of the servers is disposed in one of the other rack units and electrically connected to the power supply module and the switch.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 28, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Maw-Zan Jau, Wei-Yi Chu, Chao-Jung Chen, Tzu-Hung Wang, Chih-Ming Chen