Abstract: A fan module and computing device with the fan module are disclosed. The fan module includes a handle configured to actuate between an operation state and a release state. The handle in the release state allows a user to vertically remove the fan module from its respective fan module slot and away from the bottom panel.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.

Abstract: An electronic package is provided, in which electronic elements and at least one packaging module including a semiconductor chip and a shielding structure covering the semiconductor chip are disposed on a carrier structure, an encapsulation layer encapsulates the electronic elements and the packaging module, and a shielding layer is formed on the encapsulation layer and in contact with the shielding structure. Therefore, the packaging module includes the semiconductor chip and the shielding structure and has a chip function and a shielding wall function simultaneously.

Abstract: A connector includes a base, a latch, and a first axle element. The latch is disposed on the base. The latch includes a main portion, a front-left arm, a front-right arm, a back-left arm, and a back-right arm, wherein each of the front end of the front-left arm and the front end of the front-right arm has a hook-shaped structure, and each of the back-left arm and the back-right arm has a hole. The first axle element is pivoted to the hole of the back-left arm and the base. The back-left arm of the latch is located along the lengthwise direction of the front-left arm, and the back-left arm and the front-left arm are connected by a connecting structure.

Abstract: A fan braking structure includes a fan including a frame having an upright bearing cup, and a fan impeller having a vertical rotating shaft pivotally received in the bearing cup and provided at a free end with a groove; a braking structure located at a lower part of the bearing cup and including a brake plate and an electromagnet, and the brake plate being provided at one side with a protruded brake pin and at another side with a magnetic member; and an elastic element disposed between and pressed against a top of the shell and the brake plate. When the fan is inactive, the electromagnet is energized to produce magnetic poles that repel the magnetic member and compress the elastic element, such that the brake pin is magnetically pushed toward the rotating shaft to engage with the groove, causing the fan to brake and stop rotating inertially.

Abstract: A battery module for monitoring and suppressing battery swelling and interacting with a charging device includes a battery cell disposed in a nonconductive housing, a conductive label affixed to the nonconductive housing, a switch, and a controller. The battery cell is charged via a supply voltage from a charging device. The switch is coupled between the battery cell and the conductive label. The controller detects a resistance variation value ?R of the conductive label as result of swelling of the nonconductive housing, and generates a corresponding control voltage. As the resistance of the conductive label increases, the supply voltage may be adjusted downward according to the control voltage. If the resistance variation value ?R conductive label is greater than or equal to a predetermined threshold, the controller closes the switch, and the battery cell may then fully discharge through the conductive label.

Abstract: A fan brake structure includes a fan and a brake device. The fan has a frame body, a fan impeller and a stator. The brake device is disposed under a bottom of a bearing cup. The brake device has a driving member, a brake member and an elastic member. The elastic member abuts against one end of the brake member. The other end of the brake member has a boss body. The driving member has a spiral rail. When the driving member rotates, the boss body moves along the spiral rail, whereby the brake member linearly reciprocally moves upward to brake the fan impeller or linearly reciprocally moves downward to release the fan impeller from the braking.

Abstract: An enhancement mode high electron mobility transistor (HEMT) includes a group III-V semiconductor body, a group III-V barrier layer and a gate structure. The group III-V barrier layer is disposed on the group III-V semiconductor body, and the gate structure is a stacked structure disposed on the group III-V barrier layer. The gate structure includes a gate dielectric and a group III-V gate layer disposed on the gate dielectric, and the thickness of the gate dielectric is between 15 nm to 25 nm.

Abstract: A fan braking structure includes a fan including a frame having an upright bearing cup, and a fan impeller having a vertical rotating shaft pivotally received in the bearing cup and provided at a free end with a groove; a braking structure located at a lower part of the bearing cup and including a brake plate and an electromagnet, and the brake plate being provided at one side with a protruded brake pin and at another side with a magnetic member; and an elastic element disposed between and pressed against the brake plate and the electromagnet. When the fan is powered off, the electromagnet is energized and produces magnetic poles that magnetically repel the magnetic member, such that the brake pin is pushed by a magnetic force and the elastic element toward the rotating shaft to engage with the groove, causing the fan to brake and stop rotating inertially.

Abstract: A semiconductor structure includes a first tier, a redistribution circuit structure, and a second tier. The first tier includes at least one first die. The redistribution circuit structure is disposed on the first tier and electrically coupled to the at least one first die, where the redistribution circuit structure has a multi-layer structure and includes a vertical connection structure continuously extending from a first side of the redistribution circuit structure to a second side of the redistribution circuit structure, and the first side is opposite to the second side along a stacking direction of the first tier and the redistribution circuit structure. The second tier includes a plurality of second dies, and is disposed on and electrically coupled to the redistribution circuit structure.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A method for fabricating a high electron mobility transistor (HEMT) includes the steps of forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a gate electrode layer on the p-type semiconductor layer, and patterning the gate electrode layer to form a gate electrode. Preferably, the gate electrode includes an inclined sidewall.

Abstract: Provided is a flexible flat cable with no secondary processing adhesives. The flexible flat cable with no secondary processing adhesives includes a plurality of parallel arranged conductors, two insulation layers and two shielding layers. The two insulation layers have respective inner surfaces oppositely positioned to be adhered to sandwich the parallel arranged conductors. The two shielding layers are respectively adhered on respective outer surfaces of the two insulation layers. At least one of the inner surfaces or at least one of the outer surfaces of the two insulation layers is modified to have a modified surface layer possessing adhesibility.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A flexible flat cable includes an upper bonding adhesive layer and a lower bonding adhesive layer bonded together, a plurality of bare wires being sandwiched, an upper metal shielding layer located on an upper side of the upper bonding adhesive layer and adhesively attached to the upper bonding adhesive layer, and a lower metal shielding layer located on a lower side of the lower bonding adhesive layer and adhesively attached to the lower side of the lower bonding adhesive layer. The flexible flat cable does not need to be provided with an insulating material layer. It is small in size and simplified in structure. It not only can meet requirements of industries for characteristic impedance and insertion loss, but also can greatly reduce the cost, which in turn better satisfies the important issue of cost considerations of the industries.

Abstract: A connector assembly includes a connector and a flat cable. The connector includes a first terminal, a second terminal, a first body, a second body, a metal plate, a third body, and a shell. The first and second terminals electrically connect a first side and a second side of the flat cable respectively and are respectively contained in a first capacity slot and a first through-hole of the first body and in a second capacity slot and a second through-hole of the second body. The first and second bodies clamp the metal plate. The third body partly winds and fixes the first body and the second body, and protects a terminal conductive contact part of the flat cable connected by the first and second terminals to form the connector. The flat cable connects to the connector directly. There is no need for a fixed rigid printed circuit board.

Abstract: A semiconductor memory device includes a substrate, an isolation layer, a trench, a semiconductor active structure, and a floating gate electrode. The isolation layer is disposed on the substrate. The trench penetrates through the isolation layer and exposes a part of the substrate. The semiconductor active structure is disposed in the trench, and the floating gate electrode is disposed on the semiconductor active structure. A manufacturing method of the semiconductor memory device includes the following steps. The isolation layer is formed on the substrate. The trench is formed penetrating through the isolation layer and exposing a part of the substrate. The semiconductor active structure is formed in the trench. The floating gate electrode is formed on the semiconductor active structure.

Abstract: A semiconductor memory device includes a substrate having a first active area and a second active area in proximity to the first active area. A trench isolation region is between the first active area and the second active area. A source line region is disposed in the first active area and adjacent to the trench isolation region. An erase gate is disposed on the source line region. A floating gate is disposed on a first side of the erase gate. A first control gate is disposed on the floating gate. A first word line is disposed adjacent to the floating gate and the first control gate and insulated therefrom. A second control gate is disposed on a second side of the erase gate and directly on the trench isolation region. A second word line is disposed adjacent to the second control gate and insulated therefrom.

Abstract: A memory cell includes a substrate, a floating gate on the substrate, a control gate on the floating gate, a first dielectric layer between the floating gate and the control gate, an erase gate merged with the control gate and disposed on a first sidewall of the floating gate, a second dielectric layer between the floating gate and the erase gate, a select gate on an opposite second sidewall of the floating gate, a spacer between the select gate and the control gate and between the select gate and the floating gate, a source doping region in the substrate and adjacent to the first sidewall of the floating gate, and a drain doping region in the substrate and adjacent to the select gate.

Abstract: A semiconductor memory device includes a substrate, a plurality of memory cells and at least one strap cell between the plurality of memory cells disposed along a first direction, a plurality of bit line (BL) contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, respectively, and at least one source line contact electrically connected to a diffusion region of the strap cell. The at least one source line contact is aligned with the plurality of BL contacts in the first direction.