Abstract: An adjustable assembly apparatus includes a waveguide phase shifter and a waveguide multiplexer. The waveguide phase shifter has a first flange structure and the waveguide multiplexer has a second flange structure. The second flange structure and the first flange structure are embedded, and the polarization directions of the waveguide phase shifter and the waveguide multiplexer are orthogonal. In an embodiment, the first flange structure includes a bulge, the second flange structure includes a recess, and the bulge is embedded in the recess. The polarization directions of the bulge of the waveguide phase shifter and the recess of the waveguide multiplexer differ by 90 degrees.

Abstract: A waveguide includes a first waveguide member and a second waveguide member. The second waveguide member is combined with the first waveguide member to form a through hole. The first waveguide member includes a first shell and two first wing portions connected to the first shell, and the two first wing portions form a first plane. The second waveguide member includes a second shell and two second wing portions connected to the second shell, and the two second wing portions form a second plane. Bulged strips are formed at the inner rims of the second plane neighboring the through hole and extend along a longitudinal direction of the through hole, and the bulged strips protrude the second plane.

Abstract: In a method, apparatus and integrated circuit for improving image sharpness, the method includes the following steps: (a) labeling each of pixels in an image as one of an edge/texture type and a non-edge/texture type; (b) classifying each of the pixels that are labeled as the edge/texture type into one of a border point type, a transition point type, and a peak point type; and (c) using a shrinking/expanding filter to filter the pixels of the border point type, and subsequently using a high boost filter to first filter the pixels of the peak point type and then filter the pixels of the transition point type to sharpen the image.

Abstract: An image processing method, and an apparatus and an integrated circuit for implementing the method are adapted for use in a liquid crystal display. The method includes the steps of: determining which blocks in a decoded current frame are noisy blocks; finding, in a processed reference frame, a most similar reference block for each noisy block and generating a block velocity for each noisy block; and processing pixels that are in the noisy blocks having block velocities smaller than a liquid crystal response rate of the liquid crystal display, and that are not covered by after-images. The present invention utilizes the characteristics of liquid crystals to increase processing speed.

Abstract: A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (ECC) corresponding to the data. The ECC detector is used to get the number of error bits of each page. The controller coupled to the ECC detector is used for storing data and ECC in a first page to a second page when a number of used bytes of the ECC stored in a spare area of the first page exceeds a first predetermined value. A number of used bytes of the ECC stored in a spare area of the second page is less than the first predetermined value. The second page is a blank page.

Abstract: A method for reducing image ringing noise includes: (a) calculating a line spread function value of each pixel's luminance in an input image; (b) dividing the input image into a plurality of blocks, and calculating an average value and a maximum value of the line spread function values for all the pixels in each of the blocks; (c) based on the average value and the maximum value of the line spread function values for of each of the blocks, determining whether each of the blocks is an interfered flat block or a non-interfered block; (d) setting the pixels in the interfered flat block as a noisy pixels; (e) determining whether each pixel in the non-interfered block is an edge pixel or a non-edge pixel, and setting each the non-edge pixels in the non-interfered block as a noisy pixels; and (f) performing smoothing on each of the noisy pixels thus set, and combining smoothed pixels with the edge pixels for output as an output image.

Abstract: A waveguide comprises a connecting part, a main chamber and a buffer. The connecting part is connected to the main chamber via the buffer. The side length of the junction between the connecting part and the buffer is smaller than that of the junction between the buffer and the main chamber.

Abstract: A paper-shaped non-volatile storage device includes a top paper layer, a bottom paper layer and a flexible printed circuit board packaged between the top paper layer and the bottom paper layer. The flexible printed circuit board comprises a data-transmitting interface, a non-volatile memory controller and at least one non-volatile memory disposed thereon. Therefore, the paper-shaped non-volatile storage device features as both of traditional paper and traditional non-volatile storage devices, such as instantly writing, manually binding, and outwardly visible content as provided by the traditional paper sheets, and digital information storage, repeatable editing and rapid search capability as provided by the traditional non-volatile storage devices.

Abstract: The proposed invention discloses a card reader controlling apparatus based on Secure Digital (SD) protocol, which comprises a high-speed bus interface, at least one SD host, at least one SD connection interface and SDIO connection interface (SD/SDIO interface), at least one bridge, and at least one other specific memory card connecting interface. The card reader controlling apparatus according to the proposed invention is capable of directly accessing data from/to an input/output device compatible with the SDIO connection interface (e.g. an SD card) or one other specific memory card via the high-speed bus interface. Thus, multiple format conversions performed by other peripheral bus interfaces (such as an USB interface) as the prior art can be by-passed or eliminated.

Abstract: A multi-streaming web camera controlling system and controlling methodology are capable of providing an original video data stream and at least one compressed video data stream for displaying demands of local host and for requested video data format(s) by remote hosts, respectively. The host can selectively display the original video data stream and transmit the compressed video data stream(s) through the Internet directly in order to satisfy the video requirements of both the local host and remote hosts. The multi-streaming web camera controlling system and controlling methodology can reduce the consuming system resource of the host for processing a video data stream. Therefore, the multi-streaming web camera controlling system and controlling methodology are capable of decreasing the cost of the host and improving the performance for processing video data stream with improved quality.

Abstract: An image processing method for improving image quality by appropriately detecting ringing artifacts and reducing only the detected ringing artifacts, is an image processing method which includes: selecting, from among a plurality of pixels included in an input image, a candidate for a noise pixel included in the ringing artifacts, using luminance values of the plurality of pixels; judging whether or not the candidate selected in the selecting is the noise pixel based on whether or not a chrominance value of the candidate is included in a chrominance range corresponding to a comparison target region which is a part of the input image; and filtering the noise pixel which has been judged in the judging.

Abstract: An apparatus for controlling data access to non-volatile memory is provided, including a micro-controller and at least a memory controller. The micro-controller includes a data/address bus and a plurality of control pins. The micro-controller controls the data access. The memory controller includes a flash memory controller, a FIFO buffer and an error correction unit. The flash memory controller is connected to the control pins and the data/address bus of the micro-controller. The flash memory controller is also connected to the non-volatile memory through a non-volatile memory bus so that the flash memory controller is the data access and control interface between the micro-controller and the non-volatile memory. The FIFO buffer is connected to the micro-controller and the error correction unit to provide the buffering of data access.

Abstract: A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.

Abstract: An active clamping circuit. The active clamping circuit is applicable to a DC-to-DC conversion circuit, and has an output terminal to supply an output voltage to a load. In the active clamping circuit, a determining circuit is coupled to the DC-to-DC conversion circuit to determine the output detects the output voltage and to output a first enable signal when the output voltage is higher than a first predetermined voltage. A voltage adjustment circuit is coupled to the determining circuit to pull low the output voltage according to the first enable signal. An inductor has a first end coupled to the output terminal of the DC-to-DC conversion circuit, and a diode is coupled between the inductor and an input terminal of the DC-to-DC conversion circuit as a conductive path to channel discharge current to the input terminal of the DC-to-DC conversion circuit.

Abstract: A method for adjusting the PCI Express lane ordering is disclosed, comprising the following steps. The first packet associated with a first PCI Express lane ordering is sent to the peripheral device. The peripheral device replies the second packet associated with the second PCI Express lane ordering. Whether the PCI Express lane ordering is correct is determined in response to said second packet. The first PCI Express lane ordering is adjusted while the first PCI Express lane ordering does not match the second PCI Express lane ordering. Preferably, the adjusted PCI Express lane order matches the normal order or the reverse order. Then, reset and reinitialize the peripheral device. The resetting step can be accomplished by sending reset packets, or changing the common mode voltage level in order to reset the bridge chipset of the PC.

Abstract: An active clamping circuit. The active clamping circuit is applicable to a DC-to-DC conversion circuit, and has an output terminal to supply an output voltage to a load. In the active clamping circuit, a determining circuit is coupled to the DC-to-DC conversion circuit to determine the output detects the output voltage and to output a first enable signal when the output voltage is higher than a first predetermined voltage. A voltage adjustment circuit is coupled to the determining circuit to pull low the output voltage according to the first enable signal. An inductor has a first end coupled to the output terminal of the DC-to-DC conversion circuit, and a diode is coupled between the inductor and an input terminal of the DC-to-DC conversion circuit as a conductive path to channel discharge current to the input terminal of the DC-to-DC conversion circuit.