Abstract: A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.

Abstract: A finFET device includes a substrate, at least a first fin structure disposed on the substrate, a L-shaped insulator surrounding the first fin structure and exposing, at least partially, the sidewalls of the first fin structure, wherein the height of the L-shaped insulator is inferior to the height of the first fin structure in order to expose parts of the sidewalls surface of the first fin structure, and a gate structure disposed partially on the L-shaped insulator and partially on the first fin structure.

Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.

Abstract: A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second fin structure covered with a second mask layer, the first mask layer is removed, a gate material layer is formed and covers the first fin structure and the second mask layer, the gate material layer is patterned to result in a tri-gate structure covering the first fin structure and a double-gate structure covering the second fin structure and the second mask layer, and a source and a drain are formed in each of these two fin structures each at two sides of the gates.

Abstract: A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed. Accordingly, the present invention also relates to a field effect transistor with a fin structure, in which, the channel width is less than the source/drain width, and a gate structure has two sidewalls contacting two opposite sidewalls of a source region and a drain region, respectively.

Abstract: A method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate, in which, a substrate includes a first fin structure covered with a first mask layer and a second fin structure covered with a second mask layer, the first mask layer is removed, a gate material layer is formed and covers the first fin structure and the second mask layer, the gate material layer is patterned to result in a tri-gate structure covering the first fin structure and a double-gate structure covering the second fin structure and the second mask layer, and a source and a drain are formed in each of these two fin structures each at two sides of the gates.

Abstract: In an electric contact material of silver matrix capable of resisting arc erosion and containing no cadmium-composite, an Ag—(SnO2+In2O3) composite containing 9˜11% of (SnO2+In2O3) or an Ag—Cu oxide, composite containing 15˜25% of Cu oxide is used. The electrical contact material has a contact resistance of 5˜60 milliohms (mohm) and an arc erosion resistance capability up to 2*103˜10*103 times provided that the Vickers hardness (Hv) of the material is 100˜150, the measured current is 1˜5 amperes, and the measured voltage is 10˜20 volts. Two electrical contacts maintain an arc erosion resisting capability at the condition of a low contact resistance when the electrical contact material is formed on a surface of a metal substrate of an electric connector.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a dielectric hard mask layer, a first bottom anti-reflection coating (BARC) layer and a first photoresist layer are sequentially formed over the substrate. Next, the patterned first photoresist layer is used as a mask during an etch process to form a first trench structure. A second BARC layer is formed to fill the first trench structure and to cover the surface of the dielectric hard mask layer. A second photoresist layer is formed over the second BARC layer. The patterned second photoresist layer is used as a mask during an etch process to form a first via structure. The first trench structure and the first via structure are etched to obtain a second trench structure and a second via structure.

Abstract: A network intermediary device which determines the connection status with remote network intermediary devices by means of generating continuously connection test packets at same or different time intervals. When one remote network intermediary device does not receive the connection test packets within a predetermined timeout interval or has received fragged or damaged packets, the connection between the local network intermediary device and the remote network intermediary device is determined to be abnormal.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a barrier layer, a first dielectric layer, a second dielectric layer, a cap layer, a metal-containing hard mask layer, a dielectric hard mask layer, a first bottom anti-reflection coating (BARC) layer and a first photoresist layer are sequentially formed over the substrate. Next, the patterned first photoresist layer is used as a mask during an etch process to form a first trench structure. A second BARC layer is formed to fill the first trench structure and to cover the surface of the dielectric hard mask layer. A second photoresist layer is formed over the second BARC layer. The patterned second photoresist layer is used as a mask during an etch process to form a first via structure. The first trench structure and the first via structure are etched to obtain a second trench structure and a second via structure.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.

Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.

Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.

Abstract: A method of fabricating an unlanded via. A substrate has a metal layer formed thereon and an ARC layer is formed on the metal layer. A liner dielectric layer is formed on the ARC layer and the sidewall of the metal layer, and an insulating material layer is formed on the insulating dielectric layer. The insulating material layer is then etched back, so a surface of the insulating material layer lower than the ARC layer surface is formed. Thereafter, a protective layer is formed on the insulating material layer and the metal layer, in which the protective layer is different from the liner dielectric layer. An IMD layer is formed on the protective layer. Using the liner dielectric layer as an etching stop layer, the IMD layer and the protective layer are patterned, and then the liner dielectric layer on the metal layer is removed, such that an unlanded via opening is formed.