Patents by Inventor Chih-Jung Wang

Chih-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030129844
    Abstract: The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
    Type: Application
    Filed: November 13, 2002
    Publication date: July 10, 2003
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Jung Wang, Tong-Yu Chen
  • Publication number: 20020182874
    Abstract: A method for forming hybrid low-k film stack is disclosed, in which an organic spin-on low-k material and CVD low-k material are combined to avoid thermal stress effect. This invention also provides a method for applying hybrid low-k film stack to dual damascene process.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 5, 2002
    Inventor: Chih-Jung Wang
  • Patent number: 6124200
    Abstract: A method of fabricating an unlanded via. A substrate has a metal layer formed thereon and an ARC layer is formed on the metal layer. A liner dielectric layer is formed on the ARC layer and the sidewall of the metal layer, and an insulating material layer is formed on the insulating dielectric layer. The insulating material layer is then etched back, so a surface of the insulating material layer lower than the ARC layer surface is formed. Thereafter, a protective layer is formed on the insulating material layer and the metal layer, in which the protective layer is different from the liner dielectric layer. An IMD layer is formed on the protective layer. Using the liner dielectric layer as an etching stop layer, the IMD layer and the protective layer are patterned, and then the liner dielectric layer on the metal layer is removed, such that an unlanded via opening is formed.
    Type: Grant
    Filed: July 22, 1999
    Date of Patent: September 26, 2000
    Assignee: UTEK Semiconductor Corp
    Inventors: Chih-Jung Wang, Lu-Min Liu