Patents by Inventor Chih-Jung Wang
Chih-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12070823Abstract: A horizontal assembly press apparatus for performing a press-fit operation of a workpiece assembly along a horizontal axis includes a machine body unit, two moving units, two camera units, two pressing bed units and a processing unit. The machine body unit includes two main machine bodies defining an operating channel therebetween. The moving units are respectively and movably disposed on the main machine bodies. The camera units fetch images of the workpiece assembly entered the operating channel and output image signals. The pressing bed units are operated to press the workpiece assembly. The processing unit receives and analyzes the image signals, determines a target position of the horizontal axis, controls movement of the moving units to bring the pressing bed units to the target position, and controls movement of the pressing bed units to perform the press-fit operation of the workpiece assembly.Type: GrantFiled: March 23, 2022Date of Patent: August 27, 2024Assignee: CINKASA PRECISION INDUSTRIAL CO., LTD.Inventors: Chih-Jung Wang, Jhih-Chiang Huang, Chao-Tang Huang
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Patent number: 11848253Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: GrantFiled: November 8, 2021Date of Patent: December 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Publication number: 20230144609Abstract: A horizontal assembly press apparatus for performing a press-fit operation of a workpiece assembly along a horizontal axis includes a machine body unit, two moving units, two camera units, two pressing bed units and a processing unit. The machine body unit includes two main machine bodies defining an operating channel therebetween. The moving units are respectively and movably disposed on the main machine bodies. The camera units fetch images of the workpiece assembly entered the operating channel and output image signals. The pressing bed units are operated to press the workpiece assembly. The processing unit receives and analyzes the image signals, determines a target position of the horizontal axis, controls movement of the moving units to bring the pressing bed units to the target position, and controls movement of the pressing bed units to perform the press-fit operation of the workpiece assembly.Type: ApplicationFiled: March 23, 2022Publication date: May 11, 2023Inventors: Chih-Jung WANG, Jhih-Chiang HUANG, Chao-Tang HUANG
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Publication number: 20220068766Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: ApplicationFiled: November 8, 2021Publication date: March 3, 2022Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Patent number: 11205609Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: GrantFiled: March 31, 2020Date of Patent: December 21, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Publication number: 20210242110Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.Type: ApplicationFiled: March 31, 2020Publication date: August 5, 2021Inventors: Ching-Pin Hsu, Chih-Jung Wang, Chu-Chun Chang, Kuo-Yuh Yang, Chia-Huei Lin, Purakh Raj Verma
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Patent number: 9871123Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.Type: GrantFiled: March 3, 2015Date of Patent: January 16, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tong-Yu Chen, Chih-Jung Wang
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Patent number: 9607575Abstract: A display mode adjusting method and a display mode adjusting module executing the adjusting method are provided. The method includes the following steps: generating a saturation adjusting output color according to an input color to adjust the saturation; obtaining a relative color temperature adjusting parameter according to a target color temperature and an original optical characteristic of a display device; generating a color temperature adjusting output color according to the saturation adjusting output color and the relative color temperature adjusting parameter to adjust the color temperature; obtaining a brightness adjustment value according to the brightness of ambient light to adjust the brightness. Therefore, the display mode of the display device is adjusted to suitable for reading, which avoids the eyestrain when the users read for a long time.Type: GrantFiled: May 13, 2014Date of Patent: March 28, 2017Assignee: ASUSTeK COMPUTER INC.Inventor: Chih-Jung Wang
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Patent number: 9214384Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.Type: GrantFiled: December 24, 2014Date of Patent: December 15, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Tong-Yu Chen, Chih-Jung Wang
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Publication number: 20150179652Abstract: A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.Type: ApplicationFiled: March 5, 2015Publication date: June 25, 2015Inventors: Chih-Jung Wang, Tong-Yu Chen
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Publication number: 20150171194Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.Type: ApplicationFiled: March 3, 2015Publication date: June 18, 2015Inventors: Tong-Yu Chen, Chih-Jung Wang
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Publication number: 20150111385Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.Type: ApplicationFiled: December 24, 2014Publication date: April 23, 2015Inventors: Tong-Yu Chen, Chih-Jung Wang
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Patent number: 9012975Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.Type: GrantFiled: June 14, 2012Date of Patent: April 21, 2015Assignee: United Microelectronics Corp.Inventors: Tong-Yu Chen, Chih-Jung Wang
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Patent number: 9006107Abstract: A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.Type: GrantFiled: March 11, 2012Date of Patent: April 14, 2015Assignee: United Microelectronics Corp.Inventors: Chih-Jung Wang, Tong-Yu Chen
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Patent number: 8946078Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.Type: GrantFiled: March 22, 2012Date of Patent: February 3, 2015Assignee: United Microelectronics Corp.Inventors: Tong-Yu Chen, Chih-Jung Wang
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Patent number: 8946031Abstract: A method for fabricating a MOS device is described. A first hard mask layer is formed over a substrate. The first hard mask layer is patterned and a portion of the substrate removed to form a first patterned hard mask, and a fin structure surrounded by a trench and extending in a first direction. An insulating layer is formed at the trench bottom. A gate conductive layer is formed on the insulating layer, extending in a second direction. A first implant process is performed using the first patterned hard mask as a mask to form first S/D extension regions in the sidewalls of the fin structure. The first patterned hard mask is removed to expose the top of the fin structure, and then a second implant process is performed to form second S/D extension region therein.Type: GrantFiled: January 18, 2012Date of Patent: February 3, 2015Assignee: United Microelectronics Corp.Inventors: Chih-Jung Wang, Tong-Yu Chen
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Publication number: 20140374841Abstract: A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.Type: ApplicationFiled: September 11, 2014Publication date: December 25, 2014Inventors: Chih-Jung Wang, Tong-Yu Chen
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Publication number: 20140333656Abstract: A display mode adjusting method and a display mode adjusting module executing the adjusting method are provided. The method includes the following steps: generating a saturation adjusting output color according to an input color to adjust the saturation; obtaining a relative color temperature adjusting parameter according to a target color temperature and an original optical characteristic of a display device; generating a color temperature adjusting output color according to the saturation adjusting output color and the relative color temperature adjusting parameter to adjust the color temperature; obtaining a brightness adjustment value according to the brightness of ambient light to adjust the brightness. Therefore, the display mode of the display device is adjusted to suitable for reading, which avoids the eyestrain when the users read for a long time.Type: ApplicationFiled: May 13, 2014Publication date: November 13, 2014Applicant: ASUSTeK COMPUTER INC.Inventor: Chih-Jung WANG
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Patent number: 8871575Abstract: A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise. The trench is disposed over portions of the fin structure, and a lengthwise direction of the trench intersects a lengthwise direction of the fin structure, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed.Type: GrantFiled: October 31, 2011Date of Patent: October 28, 2014Assignee: United Microelectronics Corp.Inventors: Chih-Jung Wang, Tong-Yu Chen
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Patent number: 8803247Abstract: A fin-type field effect transistor including at least one fin-type semiconductor structure, a gate strip and a gate insulating layer is provided. The fin-type semiconductor structure is doped with a first type dopant and has a block region with a first doping concentration and a channel region with a second doping concentration. The first doping concentration is larger than the second doping concentration. The blocking region has a height. The channel region is configured above the blocking region. The gate strip is substantially perpendicular to the fin-type semiconductor structure and covers above the channel region. The gate insulating layer is disposed between the gate strip and the fin-type semiconductor structure.Type: GrantFiled: December 15, 2011Date of Patent: August 12, 2014Assignee: United Microelectronics CorporationInventors: Chih-Jung Wang, Tong-Yu Chen