Patents by Inventor Chih-Jung Wang

Chih-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10875961
    Abstract: A polycarbonate diol is provided, including three kinds of repeating diol units, wherein one of the repeating diol units is chosen from an alkoxylated diol monomer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Dairen Chemical Corporation
    Inventors: Fu-Shen Lin, June-Yen Chou, Hsing-Yun Wang, Chih-Jung Chen, Wei-Lun Hsieh
  • Publication number: 20200373401
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Patent number: 10820425
    Abstract: A display device is provided. The display device includes a display panel, a flexible circuit board, an integrated circuit, and a conductive layer. The flexible circuit board is electrically connected with the display panel and includes a plurality of conductive wires. The integrated circuit is disposed on the flexible circuit board and has a plurality of bumps. The conductive layer is disposed between the integrated circuit and the flexible circuit board and covers a periphery of the integrated circuit. In addition, the conductive layer includes an adhesive and a plurality of conductive particles distributed in the adhesive. Moreover, the bumps are electrically connected with the conductive wires through the conductive particles.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: October 27, 2020
    Assignee: Innolux Corporation
    Inventors: Wei-Cheng Chu, Chia-Cheng Liu, Chih-Yuan Lee, Chin-Lung Ting, Tong-Jung Wang
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Publication number: 20200266340
    Abstract: An integrated circuit is provided. The integrated circuit includes a metallization pattern, a dielectric layer, and plural memory devices. The metallization pattern has plural first conductive features and a second conductive feature. The dielectric layer is over the metallization pattern, in which the dielectric layer has a first portion over the first conductive features and a second portion over the second conductive feature. The memory devices are at least partially in the first portion of the dielectric layer and respectively connected with the first conductive features. The first portion of the dielectric layer has a plurality of side parts respectively surrounding the memory devices and an extending part connecting the side parts to each other, and a thickness of the second portion is greater than a thickness of the extending part of the first portion of the dielectric layer.
    Type: Application
    Filed: May 4, 2020
    Publication date: August 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Patent number: 10686030
    Abstract: A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to the semiconductor substrate, a second opening extending to a first depth that is substantially less than a thickness of the dielectric layer, and a third opening extending to a second depth that is substantially greater than the first depth. A multi-layer gate electrode is formed in the first opening. A thin resistor structure is formed in the second opening, and a connection structure is formed in the third opening, by filling the second and third openings substantially simultaneously with a resistor metal.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Jung Yen, Jen-Pan Wang, Yu-Hong Pan, Chih-Fu Chang
  • Publication number: 20200185597
    Abstract: A memory device includes an insulation layer, a memory cell region and an alignment mark region are defined on the insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, the dielectric layer is disposed within the memory cell region and the alignment mark region, a conductive via plug disposed on the interconnection structure within the memory cell region, the conductive via plug has a concave top surface, an alignment mark trench penetrating the dielectric layer within the alignment mark region, a bottom electrode disposed on the conductive via plug within the memory cell region and disposed in the alignment mark trench within the alignment mark region, and a magnetic tunnel junction (MTJ) structure disposed on the bottom electrode within the memory cell region and disposed in the alignment mark trench within the alignment mark region.
    Type: Application
    Filed: December 11, 2018
    Publication date: June 11, 2020
    Inventors: Kun-Ju Li, Hsin-Jung Liu, I-Ming Tseng, Chau-Chung Hou, Yu-Lung Shih, Fu-Chun Hsiao, Hui-Lin Wang, Tzu-Hsiang Hung, Chih-Yueh Li, Ang Chan, Jing-Yin Jhang
  • Publication number: 20200152763
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Application
    Filed: January 13, 2020
    Publication date: May 14, 2020
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 10651373
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh, Hui-Hsien Wei
  • Publication number: 20200117257
    Abstract: A power control device including a main battery, an auxiliary battery, a charging circuit, and a control circuit, for supplying power to a load is proposed. The main battery supplies power to the load. A volume, a capacity, and an output voltage of the auxiliary battery are all less than those of the main battery. The charging circuit receives a power input signal from a power supply network via a power adapter. The charging circuit generates a protection signal when changing from a first state that receives the power input signal to a second state that does not receive the power input signal. The control circuit controls the auxiliary battery to supply power to the load via a boosting circuit when receiving the protection signal, where a second output voltage outputted by the auxiliary battery is greater than or equal to a first output voltage outputted by the main battery.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 16, 2020
    Applicant: Acer Incorporated
    Inventors: Shuo-Jung Chou, Chuan-Jung Wang, Chih-Chiang Chen
  • Publication number: 20200106007
    Abstract: A method for forming an integrated circuit is provided. The method includes forming a dielectric layer over a cell region and a logic region of a substrate; forming a resistance switching layer over the dielectric layer; performing at least one etch process to pattern the resistance switching layer into a plurality of resistance switching elements in the cell region, in which a first portion of the dielectric layer in the logic region is less etched by the etch process than a second portion of the dielectric layer in the cell region.
    Type: Application
    Filed: November 16, 2018
    Publication date: April 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-Yen PENG, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH, Hui-Hsien WEI
  • Publication number: 20200106008
    Abstract: A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.
    Type: Application
    Filed: April 1, 2019
    Publication date: April 2, 2020
    Inventors: Tai-Yen Peng, Sin-Yi Yang, Chen-Jung Wang, Yu-Shu Chen, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Chih-Yuan Ting
  • Publication number: 20200091034
    Abstract: A semiconductor package is provided. The semiconductor package includes a substrate and a semiconductor die over the substrate. A heat-dissipating feature covers the substrate and the semiconductor die, and a composite thermal interface material (TIM) structure is thermally bonded between the semiconductor die and the heat-dissipating feature. The composite TIM structure includes a metal-containing matrix material layer and polymer particles embedded in the metal-containing matrix material layer.
    Type: Application
    Filed: May 22, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung-Liang SHAO, Jen-Yu WANG, Chung-Jung WU, Chih-Hang TUNG, Chen-Hua YU
  • Publication number: 20200080942
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Application
    Filed: March 16, 2018
    Publication date: March 12, 2020
    Applicant: iXensor CO., LTD.
    Inventors: Yenyu CHEN, An Cheng CHANG, Tai I CHEN, Su Tung YANG, Chih Jung HSU, Chun Cheng LIN, Min Han WANG, Shih Hao CHIU
  • Publication number: 20200066580
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Tai-Yen PENG, Chang-Sheng LIN, Chien-Chung HUANG, Yu-Shu CHEN, Sin-Yi YANG, Chen-Jung WANG, Han-Ting LIN, Chih-Yuan TING, Jyu-Horng SHIEH
  • Patent number: 10559717
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween, wherein the first semiconductor layer includes a surrounding exposed region not covered by the active layer, and the surrounding exposed region surrounds the active layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surrounding exposed region of the first semiconductor layer; an electrode layer formed on the first conductive region in the surrounding exposed region; an outside insulating layer covering a portion of the conductive layer and the electrode layer, and including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and a conductive substrate, w
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 11, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Teng Ko, Chao-Hsing Chen, Jia-Kuen Wang, Yen-Liang Kuo, Chih-Hao Chen, Wei-Jung Chung, Chih-Ming Wang, Wei-Chih Peng, Schang-Jing Hon, Yu-Yao Lin
  • Patent number: 10535748
    Abstract: Embodiments disclosed herein relate generally to forming an effective metal diffusion barrier in sidewalls of epitaxy source/drain regions. In an embodiment, a structure includes an active area having a source/drain region on a substrate, a dielectric layer over the active area and having a sidewall aligned with the sidewall of the source/drain region, and a conductive feature along the sidewall of the dielectric layer to the source/drain region. The source/drain region has a sidewall and a lateral surface extending laterally from the sidewall of the source/drain region, and the source/drain region further includes a nitrided region extending laterally from the sidewall of the source/drain region into the source/drain region. The conductive feature includes a silicide region along the lateral surface of the source/drain region and along at least a portion of the sidewall of the source/drain region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Cheng-Tung Lin, Chih-Wei Chang, Hong-Mao Lee, Ming-Hsing Tsai, Sheng-Hsuan Lin, Wei-Jung Lin, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Wei-Yip Loh, Ya-Yi Cheng
  • Patent number: 10488690
    Abstract: A display device includes a display panel, a first frame, a second frame and an adhesive element. The first frame is disposed corresponding to the display panel and includes a bottom portion and a side wall. The bottom portion is connected to the side wall. The second frame is disposed on the first frame. The display panel is disposed on a part of the second frame. The adhesive element is disposed between the first frame and the second frame. The adhesive element contacts at least a part of the bottom portion and at least a part of the side wall. An assembling method of the display device is also provided.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: November 26, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chih-Chiao Yang, Chia-Chun Yang, Chin-Cheng Kuo, Tong-Jung Wang
  • Patent number: 10475702
    Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: November 12, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Wang, Ya-Yi Cheng, I-Li Chen
  • Patent number: RE48135
    Abstract: A server system includes a rack, a power supply module, a switch, and a plurality of servers. The rack can be divided into a plurality of rack units. The rack units are parallel to each other and vertically arranged. The power supply module and the switch are disposed in close proximity to each other in at least one of the rack units. The power supply is adjacent to the rear side of the rack. The switch is adjacent to the front side of the rack. Each of the servers is disposed in one of the other rack units and electrically connected to the power supply module and the switch.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 28, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Maw-Zan Jau, Wei-Yi Chu, Chao-Jung Chen, Tzu-Hung Wang, Chih-Ming Chen