Abstract: A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.

Abstract: A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Abstract: The present invention provides a mouse device with a detection function of non-human mouse events and a detection method thereof. A driver receives a plurality of movement mouse events through a computer device from a mouse device, executes a non-human movement detection on the movement mouse events to determine each movement mouse event as a suspicious event or a human-made event, executes an interference process when the suspicious events meet a non-human critical condition, and executes the plurality of movement mouse events when the suspicious events do not meet the non-human critical condition. The present invention can effectively detect non-human movement mouse events, and execute interference on the non-human movement mouse events to deter non-human operations.

Abstract: A mouse device includes a detection function to detect non-human mouse events through encryption and a detection method thereof. A mouse retrieves variable characters, executes an encryption process on a plaintext mouse event to obtain a ciphertext mouse event based on the variable characters and fixed characters. A computer device executes a decryption process on the ciphertext mouse event to obtain the plaintext mouse event when receiving the ciphertext mouse event, executes the plaintext mouse event, and executes an interfering process when the mouse event is different or cannot be decrypted.

Abstract: A memory device includes a substrate, a bottom source structure, gate layers, dielectric layers, a contact structure and a plurality of support pillar structures. The bottom source structure is located over the substrate. The bottom source structure includes a bottom electrode layer, a dielectric stack structure and a blocking structure. The gate layers and the dielectric layers are alternately stacked over the bottom source structure. The contact structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The support pillar structure penetrates through the gate layers and the dielectric layers and extends to the bottom source structure. The dielectric stack structure of the bottom source structure surrounds each of the support pillar structures. The blocking structure of the bottom source structure is located between one of the support pillar structures and the contact structure.

Abstract: A semiconductor die includes a substrate, a semiconductor device, a back-end-of-line (BEOL) structure, and a heat dissipation structure. The substrate includes a device region and a non-device region. The BEOL structure includes a plurality of metallization layers. Each of the metallization layers includes a dielectric layer, interconnect features, and metal patterns. The interconnect features is in the dielectric layer and over the device region of the substrate, in which the interconnect features are electrically connected with the semiconductor device. The metal patterns are in the dielectric layer and over the non-device region of the substrate, in which the metal patterns are electrically isolated from the semiconductor device. The heat dissipation structure is over the non-device region of the substrate and extending through at least two of the metallization layers, in which the heat dissipation structure is in contact with the metal patterns of one of the metallization layers.

Abstract: An air cooling system for electronic devices includes a body, a thermal conduction component, and a heat dissipation fan. The body has a heat dissipation port and air inlet ports. The air inlet ports are disposed at a first housing part and a second housing part of the body. The first housing part is opposite to the second housing part. The thermal conduction component is disposed in the body and configured to contact a heat source. The heat dissipation fan is disposed in the body. The heat dissipation fan includes a first axial air inlet opening, a second axial air inlet opening, and radial air outlet openings. The first axial air inlet opening corresponds to one of the air inlet ports of the first housing part. The second axial air inlet opening corresponds to one of the air inlet ports of the second housing part.

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: A method for fabricating a semiconductor device is provided. The method includes coating a photoresist film over a target layer over a semiconductor substrate; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer along a direction tilted with respect to a normal direction of the semiconductor substrate, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.

Abstract: In an embodiment, a pattern transfer processing chamber includes a pattern transfer processing chamber and a loading area external to the pattern transfer processing chamber. The loading area is configured to transfer a wafer to or from the pattern transfer processing chamber. The loading area comprises a first region including a loadport, a second region including a load-lock between the first region and the pattern transfer processing chamber, and an embedded baking chamber configured to heat a patterned photoresist on the wafer.

Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.

Abstract: A memory device includes first and second interconnect structures, a stacked structure, a stop layer and channel pillar structures over a substrate. The stacked structure is located between the first and the second interconnection structures. The stop layer is located between the stacked structure and the second interconnect structure. Each channel pillar structure includes a channel pillar, a first channel plug and a second channel plug. The channel pillar extends through the stacked structure and the stop layer. The first channel plug is located at a first end of the channel pillar and connected to the first interconnection structure. The second channel plug is located at a second end of the channel pillar and connected to the second interconnection structure. A bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer.

Abstract: A memory device includes a substrate, a plurality of conductive layers, a plurality of dielectric layers, a memory structure, a select gate structure and a bit line contact. The conductive layers and the dielectric layers are interlaced and stacked on the substrate. The memory structure penetrates through the conductive layers and the dielectric layers, and the memory structure includes a channel structure and a conductive plug disposed on the channel structure. The select gate structure is disposed on a sidewall of the memory structure. The select gate structure includes a select gate dielectric layer and a select gate electrode surrounded by the select gate dielectric layer. A top surface of the select gate electrode is between a top surface of the conductive plug and a top surface of a topmost layer of the conductive layers. The bit line contact is electrically connected to the memory structure.

Abstract: The current disclosure includes a plasma etching system that includes a movable plasma source and a moveable wafer stage. A relative position between the movable plasma source and the movable wafer stage can be varied to set up an angle along which plasma particles of the plasma hits a wafer positioned on the wafer stage.

Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.

Abstract: In an embodiment, a method includes: placing a wafer on an implanter platen, the wafer including alignment marks; measuring a position of the wafer by measuring positions of the alignment marks with one or more cameras; determining an angular displacement between the position of the wafer and a reference position of the wafer; and rotating the implanter platen by the angular displacement.

Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.

Abstract: A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.