Patents by Inventor Chih-Kai Yang

Chih-Kai Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375778
    Abstract: A semiconductor structure disposed on a temporary carrier board is provided. Multiple adhesive layers are disposed on the temporary carrier. The semiconductor structure includes an adhesive-layer structure and a micro light-emitting element. The adhesive-layer structure includes a mending adhesive layer and a buffer layer. The mending adhesive layer is disposed on the temporary carrier board. The micro light-emitting element is disposed on the mending adhesive layer. The buffer layer is disposed between the mending adhesive layer and the micro light-emitting element. A height of the mending adhesive layer is less than a height of each of the adhesive layers in a thickness direction of the temporary carrier board. A sum of the height of the mending adhesive layer and the height of the buffer layer is greater than or equal to a height of each of the adhesive layers.
    Type: Application
    Filed: September 26, 2021
    Publication date: November 24, 2022
    Applicant: PlayNitride Display Co., Ltd.
    Inventors: Yu-Yun Lo, Chih-Kai Huang, Bo-Wei Wu, Shiang-Ning Yang
  • Publication number: 20220367559
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Yung-Lung Yang
  • Patent number: 11502123
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-kai Tsao, Yung-Lung Yang
  • Patent number: 11495681
    Abstract: A semiconductor device includes a semiconductor substrate, a recess, a first gate oxide layer, and a gate structure. The semiconductor substrate includes a first region and a second region adjacent to the first region. The recess is disposed in the first region of the semiconductor substrate, and an edge of the recess is located at an interface between the first region and the second region. At least a part of the first gate oxide layer is disposed in the recess. The first gate oxide layer includes a hump portion disposed adjacent to the edge of the recess, and a height of the hump portion is less than a depth of the recess. The gate structure is disposed on the first region and the second region of the semiconductor substrate, and the gate structure overlaps the hump portion of the first gate oxide layer in a vertical direction.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: November 8, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chang-Po Hsiung, Ching-Chung Yang, Shan-Shi Huang, Shin-Hung Li, Nien-Chung Li, Wen-Fang Lee, Chiu-Te Lee, Chih-Kai Hsu, Chun-Ya Chiu, Chin-Hung Chen, Chia-Jung Hsu, Ssu-I Fu, Yu-Hsiang Lin
  • Patent number: 11490283
    Abstract: A user equipment terminal (UE) in a wireless network calculates a measurement period for measuring the signal-to-interference-plus-noise ratio (SINR) for a serving cell within a frequency range. The calculation is based on a channel measurement resource (CMR) and an interference measurement resource (IMR). The calculation includes evaluation of a sharing factor P, which is a maximum of PCMR of the CMR and PIMR of the IMR. The PCMR and the PIMR are evaluated, at least in part, based on periodicity of the CMR and the IMR in relation to other periodic measurements performed by the UE. The UE performs a channel measurement and an interference measurement using the CMR and the IMR, respectively, over the measurement period. The UE calculates the SINR based on the channel measurement and the interference measurement; and transmits an SINR measurement report indicating the calculated SINR to a base station.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 1, 2022
    Assignee: MediaTek Inc.
    Inventors: Chih-Kai Yang, Hsuan-Li Lin, Tsang-Wei Yu
  • Publication number: 20220344153
    Abstract: A method for forming a semiconductor device is provided. The method for forming a semiconductor device is provided. The method includes coating a photoresist film over a target layer; performing a lithography process to pattern the photoresist film into a photoresist layer; performing a directional ion bombardment process to the photoresist layer, such that a carbon atomic concentration in the photoresist layer is increased; and etching the target layer using the photoresist layer as an etch mask.
    Type: Application
    Filed: August 9, 2021
    Publication date: October 27, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tien SHEN, Chih-Kai YANG, Hsiang-Ming CHANG, Chun-Yen CHANG, Ya-Hui CHANG, Wei-Ting CHIEN, Chia-Cheng CHEN, Liang-Yin CHEN
  • Publication number: 20220336367
    Abstract: A semiconductor device includes a source/drain component of a transistor. A source/drain contact is disposed over the source/drain component. A source/drain via is disposed over the source/drain contact. The source/drain via contains copper. A first liner at least partially surrounds the source/drain via. A second liner at least partially surrounds the first liner. The first liner and the second liner are disposed between the source/drain contact and the source/drain via. The first liner and the second liner have different material compositions.
    Type: Application
    Filed: September 3, 2021
    Publication date: October 20, 2022
    Inventors: Chen-Hung Tsai, Chao-Hsun Wang, Pei-Hsuan Lee, Chih-Chien Chi, Ting-Kui Chang, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11477910
    Abstract: A centrifugal fan including an impeller housing and an impeller. The impeller housing has an accommodation space, an air inlet and an air outlet. The air inlet and the air outlet are connected to the accommodation space. The impeller is located in the accommodation space. The impeller includes a hub, a plurality of blades, and at least one heat conductive annular portion. The hub is rotatably disposed in the impeller housing. The plurality of blades are connected to an outer circumferential surface of the hub. The at least one heat conductive annular portion is connected to the plurality of blades.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 18, 2022
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Shin-Hsin Hsien, Chih-Kai Yang
  • Patent number: 11475563
    Abstract: A benign tumor development trend assessment system includes an image outputting device and a server computing device. The image outputting device outputs first/second images captured from the same position in a benign tumor. The server computing device includes an image receiving module, an image pre-processing module, a target extracting module, a feature extracting module and a trend analyzing module. The image receiving module receives the first/second images. The image pre-processing module pre-processes the first/second images to obtain first/second local images. The target extracting module automatically detects and delineates tumor regions from the first/second local images to obtain first/second region of interest (ROI) images. The feature extracting module automatically identifies the first/second ROI images to obtain at least one first/second features. The trend analyzing module analyzes the first/second features to obtain a tumor development trend result.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: October 18, 2022
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Cheng-Chia Lee, Huai-Che Yang, Wen-Yuh Chung, Chih-Chun Wu, Wan-Yuo Guo, Wei-Kai Lee, Tzu-Hsuan Huang, Chun-Yi Lin, Chia-Feng Lu, Yu-Te Wu
  • Publication number: 20220328324
    Abstract: In a method of forming a pattern over a semiconductor substrate, a target layer to be patterned is formed over a substrate, a mask pattern including an opening is formed in a mask layer, a shifting film is formed in an inner sidewall of the opening, a one-directional etching operation is performed to remove a part of the shifting film and a part of the mask layer to form a shifted opening, and the target layer is patterned by using the mask layer with the shifted opening as an etching mask. A location of the shifted opening is laterally shifted from an original location of the opening.
    Type: Application
    Filed: April 9, 2021
    Publication date: October 13, 2022
    Inventors: Yi-Chen LO, Yi-Shan CHEN, Chih-Kai YANG, Pinyen LIN
  • Publication number: 20220302168
    Abstract: Provided is a memory device including a stack structure, a first set of vertical channel structures, a second set of vertical channel structures and a first slit. The stack structure is disposed on a substrate, wherein a top surface of the substrate is parallel to a plane defined by a X direction and a Y direction perpendicular to the X direction. The first set of vertical channel structures and the second set of vertical channel structures are arranged along the Y direction and penetrating through the stack structure along a Z direction vertical to the plane to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure along the Z direction to expose the substrate, wherein the first slit includes a plurality of first sub-slits discretely disposed along the X direction.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Publication number: 20220293448
    Abstract: A method of correcting a misalignment of a wafer on a wafer holder and an apparatus for performing the same are disclosed. In an embodiment, a semiconductor alignment apparatus includes a wafer stage; a wafer holder over the wafer stage; a first position detector configured to detect an alignment of a wafer over the wafer holder in a first direction; a second position detector configured to detect an alignment of the wafer over the wafer holder in a second direction; and a rotational detector configured to detect a rotational alignment of the wafer over the wafer holder.
    Type: Application
    Filed: March 12, 2021
    Publication date: September 15, 2022
    Inventors: Chia-Cheng Chen, Chih-Kai Yang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11411020
    Abstract: Provided is a memory device including a substrate, a stack structure, a first set of vertical channel structures, a second set of vertical channel structures, and a first slit. The stack structure is disposed on the substrate. The first and second sets of vertical channel structures are arranged along a Y direction and penetrate through the stack structure to contact the substrate. The first slit is disposed between the first and second sets of vertical channel structures, and penetrates through the stack structure to expose the substrate. The first slit includes a plurality of first sub-slits discretely disposed along a X direction.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 9, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Kai Yang, Tzung-Ting Han
  • Patent number: 11397453
    Abstract: A heat dissipation system includes a single fan, first and second heat sources, first, second, and third heat pipes, and first and second heat dissipation arrays. The first heat pipe is thermally coupled with the first heat source. The second heat pipe is thermally coupled with the second heat source. The third heat pipe has a first position thermally coupled with the first heat pipe and a second position thermally coupled with the second heat pipe. The first heat dissipation array is arranged around the first position and thermally coupled with the third heat pipe. The second heat dissipation array is arranged around the second position and thermally coupled with the third heat pipe. The single fan is between the first and second heat sources, and configured to blow airflows towards the first and second heat sources, the first and second heat dissipation arrays.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: July 26, 2022
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Jyun-Ji Lu, Sheng-Chieh Hsu, Chih-Kai Yang
  • Publication number: 20220223634
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first image sensing element and a second image sensing element arranged over a substrate. A first micro-lens is arranged over the first image sensing element, and a second micro-lens is arranged over the second image sensing element. A composite deep trench isolation structure is arranged between the first and second image sensing elements. The composite deep trench isolation structure includes a lower portion arranged over the substrate and an upper portion arranged over the lower portion. The lower portion includes a first material, and the upper portion includes a second material that has a higher reflectivity than the first material.
    Type: Application
    Filed: January 8, 2021
    Publication date: July 14, 2022
    Inventors: Che Wei Yang, Sheng-Chan Li, Tsun-Kai Tsao, Chih-Cheng Shih, Sheng-Chau Chen, Cheng-Yuan Tsai
  • Publication number: 20220164624
    Abstract: The present disclosure provides a card shaped mobile payment device, which includes a card shaped casing and an offline payment execution module configured for executing an offline payment operation and disposed in the card shaped casing. The offline payment execution module includes a display module, a security chip, an antenna unit and a central control unit. The display module is used for displaying card information; the security chip is used for generating a token information, which is time-sensitive, and executing a transaction procedure. The antenna unit is electrically connected to the security chip for providing the token information to a transaction device. The central control unit activates the security chip according to a received identity authentication result, and provides a card index information corresponding to the card information to the security chip, so as to access a stored card credential and generate the token information.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 26, 2022
    Inventors: MENG-JEN CHENG, CHIH-KAI YANG
  • Publication number: 20220164800
    Abstract: The present disclosure provides a card shaped mobile payment device, which includes a card shaped casing and an offline payment execution module configured for executing an offline payment operation and disposed in the card shaped casing. The offline payment execution module includes a display module, a security chip, an antenna unit and a central control unit. The display module is used for displaying card information; the security chip is used for generating a token information, which is time-sensitive, and executing a transaction procedure. The antenna unit is electrically connected to the security chip for providing the token information to a transaction device. The central control unit activates the security chip according to a received identity authentication result, and provides a card index information corresponding to the card information to the security chip, so as to access a stored card credential and generate the token information.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 26, 2022
    Inventors: MENG-JEN CHENG, CHIH-KAI YANG
  • Publication number: 20220165747
    Abstract: A three-dimensional memory device and a method of manufacturing a three-dimensional memory device are provided. The method includes providing a precursor structure including a substrate, a multi-layered stack, a plurality of vertical channel pillars and a barrier structure. A first slit and a second slit are then formed in the multi-layered stack and the substrate along a first direction, in which the first slit and the second slit have a pitch between thereof, and the second slit cuts the barrier structure. A portion of the second insulating layers is then replaced with a plurality of conductive layers. A first slit structure and a second slit structure are then formed in the first slit and the second slit, in which the first slit structure and the second slit structure separate the vertical channel pillars in a second direction that is different from the first direction.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Inventors: Chih-Kai YANG, Tzung-Ting HAN
  • Patent number: 11337317
    Abstract: The invention provides a server device. The server device includes a casing, an electronic assembly, and a heat dissipation assembly. The casing includes a housing and a partition. The partition is disposed in the housing and forms an accommodation space and a heat dissipation space in the housing that are not communicated with each other. The housing has a plurality of first vent holes communicated with the heat dissipation space. The electronic assembly is located in the accommodation space. The heat dissipation assembly includes a heat dissipation component and a heat pipe. The heat dissipation component is located in the heat dissipation space. The heat pipe includes a heat absorption portion and a condensation portion connected to each other. The heat pipe is disposed through the partition, the heat absorption portion is thermally coupled to the electronic assembly, and the condensation portion is coupled to the heat dissipation component.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 17, 2022
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chih-Kai Yang, Ming-Hung Lin, Chung-Yi Huang, Yu-Wei Liu
  • Publication number: 20220131292
    Abstract: A connector assembly for mounting a chip module to a printed circuit board (PCB) includes: a seating mechanism including a socket connector, a metallic seat frame, and a metallic load plate; a back plate; and plural fasteners extending through the seating mechanism, the PCB, and the back plate to fasten the seating mechanism and the back plate on two opposite sides of the PCB, wherein the back plate has a curved inner region and a flat outer region and the fasteners extend through the flat outer region of the back plate.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 28, 2022
    Inventors: SHAN-YONG CHENG, CHIH-KAI YANG