Patents by Inventor Chih-Kang Han
Chih-Kang Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948881Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.Type: GrantFiled: July 8, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20230335426Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: ApplicationFiled: June 16, 2023Publication date: October 19, 2023Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20210335708Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: July 8, 2021Publication date: October 28, 2021Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
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Patent number: 11069614Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.Type: GrantFiled: May 8, 2020Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20210202290Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: ApplicationFiled: March 15, 2021Publication date: July 1, 2021Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20210098434Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Patent number: 10950478Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: GrantFiled: May 13, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Patent number: 10867973Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: GrantFiled: July 31, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20200273795Abstract: A semiconductor structure includes a die, a molding surrounding the die, a first dielectric layer disposed over the die and the molding, and a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding. A material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer. In some embodiments, the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.Type: ApplicationFiled: May 8, 2020Publication date: August 27, 2020Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
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Patent number: 10692809Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.Type: GrantFiled: October 29, 2018Date of Patent: June 23, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Patent number: 10529697Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: GrantFiled: December 1, 2016Date of Patent: January 7, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20190267274Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Patent number: 10290590Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.Type: GrantFiled: April 12, 2017Date of Patent: May 14, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shin-Puu Jeng, Tzu-Jui Fang, Hsi-Kuei Cheng, Chih-Kang Han, Yi-Jen Lai, Hsien-Wen Liu, Yi-Jou Lin
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Patent number: 10290530Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: GrantFiled: February 12, 2018Date of Patent: May 14, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20190074248Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.Type: ApplicationFiled: October 29, 2018Publication date: March 7, 2019Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
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Publication number: 20180350784Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: ApplicationFiled: July 31, 2018Publication date: December 6, 2018Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Patent number: 10128182Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.Type: GrantFiled: January 19, 2017Date of Patent: November 13, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
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Publication number: 20180174937Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.Type: ApplicationFiled: February 12, 2018Publication date: June 21, 2018Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
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Publication number: 20180151512Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.Type: ApplicationFiled: April 12, 2017Publication date: May 31, 2018Inventors: SHIN-PUU JENG, TZU-JUI FANG, HSI-KUEI CHENG, CHIH-KANG HAN, YI-JEN LAI, HSIEN-WEN LIU, YI-JOU LIN
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Publication number: 20180082988Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.Type: ApplicationFiled: December 1, 2016Publication date: March 22, 2018Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang