Patents by Inventor Chih-Kang Han

Chih-Kang Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190267274
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10290530
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10290590
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shin-Puu Jeng, Tzu-Jui Fang, Hsi-Kuei Cheng, Chih-Kang Han, Yi-Jen Lai, Hsien-Wen Liu, Yi-Jou Lin
  • Publication number: 20190074248
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a substrate, disposing a die over the substrate, forming a molding over the substrate and around the die, disposing a first dielectric layer over the die and the molding, curing the first dielectric layer under a first curing condition, disposing a second dielectric layer over the first dielectric layer, and curing the first dielectric layer and the second dielectric layer under the first curing condition.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
  • Publication number: 20180350784
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: July 31, 2018
    Publication date: December 6, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 10128182
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: November 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Hsi-Kuei Cheng, Chih-Kang Han, Ching-Fu Chang, Hsin-Chieh Huang
  • Publication number: 20180174937
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: February 12, 2018
    Publication date: June 21, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180151512
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Application
    Filed: April 12, 2017
    Publication date: May 31, 2018
    Inventors: SHIN-PUU JENG, TZU-JUI FANG, HSI-KUEI CHENG, CHIH-KANG HAN, YI-JEN LAI, HSIEN-WEN LIU, YI-JOU LIN
  • Publication number: 20180082988
    Abstract: An embodiment is a structure including a first package including a first die, and a molding compound at least laterally encapsulating the first die, a second package bonded to the first package with a first set of conductive connectors, the second package comprising a second die, and an underfill between the first package and the second package and surrounding the first set of conductive connectors, the underfill having a first portion extending up along a sidewall of the second package, the first portion having a first sidewall, the first sidewall having a curved portion and a planar portion.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 22, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180082917
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Application
    Filed: December 23, 2016
    Publication date: March 22, 2018
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Patent number: 9922896
    Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Kuei Cheng, Ching Fu Chang, Chih-Kang Han, Hsin-Chieh Huang
  • Publication number: 20180076129
    Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.
    Type: Application
    Filed: January 19, 2017
    Publication date: March 15, 2018
    Inventors: HSI-KUEI CHENG, CHIH-KANG HAN, CHING-FU CHANG, HSIN-CHIEH HUANG
  • Patent number: 9456147
    Abstract: A video generating system includes: a plurality of image sensors, arranged to generate a plurality of images and a plurality of synchronization signals corresponding to the images; a combining circuit, coupled to the image sensors, arranged to generate a plurality of output images according to the images, and generate a plurality of output synchronization signals corresponding to the output images according to the synchronization signals; and a bus, coupled between the image sensors and the combining circuit, arranged to perform signal transmission. The image sensors comprise a first image sensor and a second image sensor; and when the combining circuit receives image data of at least a first image generated by the first image sensor, the combining circuit does not receive image data of at least a second image generated by the second image sensor at the same time.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: September 27, 2016
    Assignee: PixArt Imaging Inc.
    Inventors: Chih-Kang Han, En-Feng Hsu
  • Patent number: 9210449
    Abstract: A video generating system and a video generating method, which combine images generated by a plurality of different image sensors to generate output images, are provided. In the inventive video generating system and method, the image sensors share a signal transmission interface to transmit image data and synchronization signals in a time-shared manner to reduce the complexity of the signal transmission interface.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: December 8, 2015
    Assignee: PixArt Imaging Inc.
    Inventors: Chih-Kang Han, En-Feng Hsu
  • Publication number: 20150237267
    Abstract: A video generating system includes: a plurality of image sensors, arranged to generate a plurality of images and a plurality of synchronization signals corresponding to the images; a combining circuit, coupled to the image sensors, arranged to generate a plurality of output images according to the images, and generate a plurality of output synchronization signals corresponding to the output images according to the synchronization signals; and a bus, coupled between the image sensors and the combining circuit, arranged to perform signal transmission. The image sensors comprise a first image sensor and a second image sensor; and when the combining circuit receives image data of at least a first image generated by the first image sensor, the combining circuit does not receive image data of at least a second image generated by the second image sensor at the same time.
    Type: Application
    Filed: May 4, 2015
    Publication date: August 20, 2015
    Inventors: Chih-Kang Han, En-Feng Hsu
  • Patent number: 8952534
    Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
  • Publication number: 20140192213
    Abstract: A video generating system and a video generating method, which combine images generated by a plurality of different image sensors to generate output images, are provided. In the inventive video generating system and method, the image sensors share a signal transmission interface to transmit image data and synchronization signals in a time-shared manner to reduce the complexity of the signal transmission interface.
    Type: Application
    Filed: June 25, 2013
    Publication date: July 10, 2014
    Inventors: Chih-Kang Han, En-Feng Hsu
  • Publication number: 20140070409
    Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 13, 2014
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen LAI, Chih-Kang HAN, Chien-Pin CHAN, Chih-Yuan CHIEN, Huai-Tei YANG
  • Patent number: 8610270
    Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: December 17, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang
  • Publication number: 20110193219
    Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.
    Type: Application
    Filed: February 9, 2010
    Publication date: August 11, 2011
    Applicant: TAIWAN SEIMCONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen LAI, Chih-Kang Han, Chien-Pin Chan, Chih-Yuan Chien, Huai-Tei Yang