Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

Abstract: A semiconductor structure includes a substrate; a die disposed over the substrate, and including a die pad, a conductive via disposed over the die pad and a dielectric material surrounding the conductive via; a molding disposed over the substrate and surrounding the die; a lower dielectric layer disposed nearer the substrate and over the dielectric material and the molding; and an upper dielectric layer disposed further the substrate and over the lower dielectric layer, wherein a material content ratio in the upper dielectric layer is substantially greater than that in the lower dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the upper dielectric layer and the lower dielectric layer.

Abstract: A video generating system includes: a plurality of image sensors, arranged to generate a plurality of images and a plurality of synchronization signals corresponding to the images; a combining circuit, coupled to the image sensors, arranged to generate a plurality of output images according to the images, and generate a plurality of output synchronization signals corresponding to the output images according to the synchronization signals; and a bus, coupled between the image sensors and the combining circuit, arranged to perform signal transmission. The image sensors comprise a first image sensor and a second image sensor; and when the combining circuit receives image data of at least a first image generated by the first image sensor, the combining circuit does not receive image data of at least a second image generated by the second image sensor at the same time.

Abstract: A video generating system and a video generating method, which combine images generated by a plurality of different image sensors to generate output images, are provided. In the inventive video generating system and method, the image sensors share a signal transmission interface to transmit image data and synchronization signals in a time-shared manner to reduce the complexity of the signal transmission interface.

Abstract: A video generating system includes: a plurality of image sensors, arranged to generate a plurality of images and a plurality of synchronization signals corresponding to the images; a combining circuit, coupled to the image sensors, arranged to generate a plurality of output images according to the images, and generate a plurality of output synchronization signals corresponding to the output images according to the synchronization signals; and a bus, coupled between the image sensors and the combining circuit, arranged to perform signal transmission. The image sensors comprise a first image sensor and a second image sensor; and when the combining circuit receives image data of at least a first image generated by the first image sensor, the combining circuit does not receive image data of at least a second image generated by the second image sensor at the same time.

Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.

Abstract: A video generating system and a video generating method, which combine images generated by a plurality of different image sensors to generate output images, are provided. In the inventive video generating system and method, the image sensors share a signal transmission interface to transmit image data and synchronization signals in a time-shared manner to reduce the complexity of the signal transmission interface.

Abstract: A semiconductor device includes a semiconductor substrate, a pad region on the semiconductor substrate, a passivation layer over the semiconductor substrate and at least a portion of the pad region, and a bump structure overlying the pad region. The passivation layer has an opening defined therein to expose at least another portion of the pad region. The bump structure is electrically connected to the pad region via the opening. The bump structure includes a copper layer and a SnAg layer overlying the copper layer. The SnAg layer has a melting temperature higher than the eutectic temperature of Sn and Ag.

Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.

Abstract: A semiconductor device includes a bump structure over a pad region. The bump structure includes a copper layer and a lead-free solder layer over the copper layer. The lead-free solder layer is a SnAg layer, and the Ag content in the SnAg layer is less than 1.6 weight percent.