Patents by Inventor Chih-Kang Yeh

Chih-Kang Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090248961
    Abstract: A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.
    Type: Application
    Filed: August 6, 2008
    Publication date: October 1, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Kuo-Yi Cheng, Chih-Kang Yeh
  • Publication number: 20090217136
    Abstract: A storage apparatus is provided. The controller of the storage apparatus includes an error correction module and a data disordering module. The error correction module is configured to perform an error correction procedure for a data packet to be written into a flash memory module of the storage apparatus for generating sequence data codes containing the data packet and corresponding error correcting codes, wherein the data packet includes a data area recording data to be written and a spare area recording data related to the data packet. The data disordering module is configured to convert the sequence data codes into non-sequence data codes, wherein the data of the data area and the spare area and error correcting codes are dispersed in the non-sequence data codes. Accordingly, it is possible to effectively increase the safety of the data packet.
    Type: Application
    Filed: May 29, 2008
    Publication date: August 27, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kuo-Yi Cheng, Chih-Kang Yeh
  • Publication number: 20090198875
    Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.
    Type: Application
    Filed: March 27, 2008
    Publication date: August 6, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chien-Hua Chu, Chih-Kang Yeh, Jian-Yo Su, Jui-Hsien Chang
  • Publication number: 20090175075
    Abstract: A flash memory storage apparatus including a multi level cell (MLC) NAND flash memory, a flash memory controller, and a host transmission bus is provided. The MLC NAND flash memory includes a plurality of blocks for storing data, wherein each of the blocks has an upper page and a lower page, and the writing speed of the lower page is faster than that of the upper page. The flash memory controller is electrically connected to the MLC NAND flash memory and is used for executing storage mode switching steps. The host transmission bus is electrically connected to the flash memory controller and is used for communicating with a host. The flash memory storage apparatus provided by the present invention can provide multiple storage modes in order to store different data.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 9, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chih-Jen Lee
  • Publication number: 20090172255
    Abstract: A wear leveling method for a multi level cell (MLC) NAND flash memory is provided. The flash memory includes a first zone and a second zone respectively having a plurality of blocks, wherein each of the blocks includes an upper page and a lower page. The wear leveling method includes: respectively determining whether to start a block swapping operation of a wear leveling process in the first zone and the second zone of the flash memory according to different start-up conditions; and respectively performing the block swapping operation in the first zone and the second zone, wherein the blocks in the first zone are accessed by using only the lower pages, and the blocks in the second zone are accessed by using both the upper pages and the lower pages. Thereby, the lifespan of the flash memory is effectively prolonged and meaningless consumption of system resources is avoided.
    Type: Application
    Filed: March 12, 2008
    Publication date: July 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Publication number: 20090150597
    Abstract: A data writing method for a flash memory is provided. The data writing method includes: dividing a new data into at lease one sub-data by the length of a writing unit; selecting one of a plurality of spare blocks from the flash memory as a substitute block for substituting a data block, wherein the new data is to be written into the data block; sequentially writing the sub-data having the length of the writing unit into the substitute block in the writing unit; and storing the sub-data not having the length of the writing unit into a temporary area. The writing efficiency of the flash memory can be improved by temporarily storing the sub-data not having the length of the writing unit into the temporary area and then writing the sub-data not having the length of the writing unit with subsequent data into the substitute block.
    Type: Application
    Filed: March 20, 2008
    Publication date: June 11, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jiunn-Yeong Yang, Jui-Hsien Chang, Chien-Hua Chu, Jian-Yo Su, Chih-Kang Yeh
  • Publication number: 20090106484
    Abstract: A data writing method for a non-volatile memory is provided, wherein the non-volatile memory includes a data area and a spare area. In the data writing method, a plurality of blocks in a substitution area of the non-volatile memory is respectively used for substituting a plurality of blocks in the data area, wherein data to be written into the blocks in the data area is written into the blocks in the substitution area, and the blocks in the substitution area are selected from the spare area of the non-volatile memory. A plurality of temporary blocks of the non-volatile memory is used as a temporary area of the blocks in the substitution area, wherein the temporary area is used for temporarily storing the data to be written into the blocks in the substitution area.
    Type: Application
    Filed: February 4, 2008
    Publication date: April 23, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu, Jia-Yi Fu
  • Publication number: 20090094409
    Abstract: A wear leveling method for non-volatile memory is provided, by which the non-volatile memory is substantially divided into a plurality of blocks and the blocks are grouped into a data area and a spare area. The method includes selecting a block based on an erased sequence when getting the block from the spare area. The method also includes performing a wear leveling procedure.
    Type: Application
    Filed: January 22, 2008
    Publication date: April 9, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Chih-Kang Yeh, Chien-Hua Chu
  • Publication number: 20090091978
    Abstract: A wear leveling method under limited system resources is provided, the wear levelling method is suitable for a non-volatile memory, the non-volatile memory is substantially divided into a plurality of blocks, and the blocks are at least grouped into a data area, a spare area and a substitution-transient area. The blocks within the data area may be divided into a plurality of lately-used blocks and a plurality of lately-unused blocks. The method includes only recording erase times of the lately-used blocks and blocks within the spare area and selecting a block used for the substitution-transient area is selected from the spare area according to a judgment condition of erase times of another block within the spare area plus a first threshold value. The method also includes performing a wear leveling procedure. Wherein, the selected block and the other block are selected in a random mode or a sequential mode.
    Type: Application
    Filed: January 14, 2008
    Publication date: April 9, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh
  • Publication number: 20090089485
    Abstract: A wear leveling method for a non-volatile memory is provided. The non-volatile memory is substantially divided into a plurality of blocks, and these blocks are grouped into at least a data area, a spare area, a substitute area, and a temporary area. The wear leveling method includes selecting blocks from the spare area according to different purposes and executing a wear leveling procedure.
    Type: Application
    Filed: January 29, 2008
    Publication date: April 2, 2009
    Applicant: PHISON ELECTRONICS CORP.
    Inventor: Chih-Kang Yeh