Abstract: A semiconductor structure includes an isolation structure formed on a substrate, a gate-all-around transistor structure formed on the isolation structure, a via electrically coupled to a gate terminal of the gate-all-around transistor structure, and a buried conductive pad formed within the isolation structure and electrically coupled to the via. The buried conductive pad can extend through the isolation structure in two dimensions, such as in both a vertical dimension and a horizontal dimension. The semiconductor structure can provide advantages in terms of routing flexibility, among other possible advantages.

Abstract: A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

Abstract: An IC device includes first and second bit circuits adjacent to each other along a row direction, third and fourth bit circuits adjacent to each other along the row direction, and a first column of output pins aligned in a column direction. The first and second bit circuits include first through fourth power rails and first through sixth active areas extending in the row direction, and the third and fourth bit circuits include the fourth power rail, fifth through seventh power rails, and seventh through twelfth active areas extending in the row direction. The first column of output pins includes first and second output pins adjacent to the second bit circuit and coupled to the respective first and second bit circuits and third and fourth output pins adjacent to the fourth bit circuit and coupled to the respective third and fourth bit circuits.

Abstract: An integrated circuit includes a set of transistors including a set of active regions, a set of power rails, a first set of conductors and a first conductor. The set of active regions extends in a first direction, and is on a first level. The set of power rails extends in the first direction and is on a second level. The set of power rails has a first width. The first set of conductors extends in the first direction, is on the second level, and overlaps the set of active regions. The first set of conductors has a second width. The first conductor extends in the first direction, is on the second level and is between the first set of conductors. The first conductor has the first width, electrically couples a first transistor of the set of transistors to a second transistor of the set of transistors.

Abstract: A method, comprising forming an integrated circuit over a first power line, wherein the integrated circuit comprises a first transistor having a first active region and a first gate structure in contact with the first active region, wherein the first active region has first source/drain regions; a second transistor over the first transistor, and having a second active region and a second gate structure in contact with the second active region, wherein the second active region has second source/drain regions, wherein the first power line is electrically connected to one of the first source/drain regions of the first active region of the second transistor; and a second power line over the second transistor, wherein the second power line is electrically connected to one of the second source/drain regions of second active region of the second transistor.

Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. A distance from a first horizontal cell boundary to a proximal edge of the first conductor segment is larger than a distance from a second horizontal cell boundary to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.

Abstract: A semiconductor device including a semiconductor chip formed from a semiconductive material and a cover formed from a conductive material is provided. The semiconductor chip and cover are bonded with a thermal interface material composition that includes metal particles dispersed in a resin or resin blend and a silane-based adhesion promoter. The TIM composition may also include a rubber and a curing agent. Methods of making semiconductor devices are also provided.

Abstract: A semiconductor device or structure includes a first pattern metal layer disposed between a first supply metal tract and a second supply metal tract, the first pattern metal layer comprising an internal route and a power route. A follow pin couples the first supply metal to the power route. The first supply metal tract comprises a first metal and a follow pin comprises a second metal.

Abstract: A connecting structure includes a case, a rotating shaft, and a cable organizer. The case includes a hollow shell and an assembly plate. The assembly plate is accommodated in the hollow shell, and two through holes are formed between two opposite side edges of the assembly plate and an inner wall of the hollow shell. The rotating shaft is assembled to one side of the assembly plate. The cable organizer includes a tubular body, a spacer, and two inserts. The spacer is located at one end of the tubular body, and the two inserts are located at two opposite sides of another end of the tubular body. When the cable organizer is assembled to the case from the other side of the assembly plate, the two inserts respectively penetrate through the two through holes and are engaged with and fixed to the inner wall of the hollow shell.

Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.

Abstract: A glue spreader is disclosed. It is a tubular structure with a body. The body tapers from a first open end to a second open end. A cross-sectional shape of the body gradually changes from a perfect circle at the first open end to an oblate circle at the second open end. The second open end forms a flow guiding curved plate outwards, the flow guiding curved plate extends in a direction vertical to an extending direction of the body and forms two symmetrical curved surfaces, and a straight-line section is formed at the end of each curved surface. The first open end is used to connect to a bottle mouth of a glue bottle of an adhesive glue.

Abstract: An integrated circuit includes a first active region, a first contact, a first and second conductor and a first and second via. The first active region extends in a first direction, and is on a first level of a substrate. The first contact extends in a second direction, is on a second level, and overlaps the first active region. The first conductor extends in the first direction, overlaps the first contact, and is on a third level. The second conductor extends in the first direction, is on the third level, overlaps the first contact, and is separated from the first conductor in the second direction. The first via is between the first contact and first conductor, and electrically couples the first contact and the first conductor together. The second via is between the first contact and the second conductor, and electrically couples the first contact and the second conductor together.

Abstract: An integrated circuit (IC) device includes a first transistor positioned on a front side of a semiconductor substrate, the first transistor including a first gate electrode, first and second epitaxial regions, a first channel extending between the first and second epitaxial regions and through the first gate electrode, and first and second metal-like defined (MD) segments directly overlying the respective first and second epitaxial regions. A first power rail is positioned on a back side of the semiconductor substrate, a first via structure extends from the first epitaxial region to the first power rail, and a second via structure extends from the first MD segment to the first power rail.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a second-type active-region semiconductor structure stacked with the first-type active-region semiconductor structure. The integrated circuit device also includes a back-side power node, a back-side power rail, and a back-side signal line in a back-side conductive layer. The integrated circuit device still includes a top-to-bottom via-connector and a source conductive segment intersecting the first-type active-region semiconductor structure at a source region of a transistor. The source conductive segment is conductively connected to a front-side power rail through a front-side terminal via-connector. The top-to-bottom via-connector is connected between the source conductive segment and the back-side power node.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: A method includes fabricating a first-voltage underlayer power rail conductively connecting to the source region of a first-type transistor and fabricating a second-voltage underlayer power rail conductively connecting to the source region of a second-type transistor. Each of the first-voltage and second-voltage underlayer power rails extends in a first direction. The method also includes patterning a first connection layer to form a first-voltage power rail and a second-voltage power rail extending in the second direction which is perpendicular to the first direction. The first-voltage power rail is directly connected with the first-voltage underlayer power rail through a first via-connector and the second-voltage power rail is directly connected with the second-voltage underlayer power rail through a second via-connector.

Abstract: A semiconductor structure includes a first transistor, a second transistor, a first dummy source/drain, a third transistor, a fourth transistor, and a second dummy source/drain. The first transistor and a second transistor adjacent to the first transistor are at a first elevation. The first dummy source/drain is disposed at the first elevation. The third transistor and a fourth transistor adjacent to the third transistor, are at a second elevation different from the first elevation. The second dummy source/drain is disposed at the second elevation. The second transistor is vertically aligned with the third transistor. The first dummy source/drain is vertically aligned with a source/drain of the fourth transistor. The second dummy source/drain is vertically aligned with a source/drain of the first transistor. The gate structure between the second dummy source/drain and a source/drain of the third transistor is absent. A method for manufacturing a semiconductor structure is also provided.

Abstract: An integrated circuit includes a set of active regions, a first set of contacts, a first gate, a first set of power rails, and a first set of vias. The first set of contacts overlaps the set of active regions, and a first and second cell boundary. The first gate overlaps the set of active regions, not overlapping the first and second cell boundary, and is between the first set of contacts. The first set of power rails is configured to supply a first or second supply voltage, and overlaps the first gate. The first set of vias is between the first gate and the first set of power rails, and electrically couples the first gate and the first set of power rails together. At least one active region of the set of active regions extends continuously through the first and second cell boundary.

Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.