Abstract: An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.

Abstract: A semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a third source/drain structure and a fourth source/drain structure of a second transistor. The second source/drain structure and the third source/drain structure merges as a common source/drain structure. The semiconductor device includes a first interconnect structure extending along a first lateral direction and disposed above the common source/drain structure. The semiconductor device includes a first dielectric structure interposed between the first interconnect structure and the common source/drain structure.

Abstract: Provided is an electronic device, including a housing, a fixing hole, a platform and a sensor. The fixing hole is located at the housing and configured to detachably fix an identification element. The platform extends outward from the lower edge of the fixing hole. The sensor is disposed on the platform and configured to communicate with the identification element.

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A human condition detection device comprises a depth image-taking module for taking a depth image of a target area. A millimeter-wave radar module detects breaths or heartbeats in the target area to provide a signal. A thermal image-taking module takes a thermal image of the target area. A processor module determines whether a person is in the target area based on the depth image. The processor module determines whether there is any breath or heartbeat based on the signal if a person is in the target area. The processor module determines whether there is any abnormal vital sign of the person in the target area based on the signal and the thermal image if there is a breath or heartbeat in the target area. The processor module actuates the warning module to provide a warning if there is an abnormal vital sign of the person in the target area.

Abstract: A backlit keyboard includes key switches and a backlight module. The backlight module includes a light guide plate, a reflecting surface, and at least one light-emitting device. The light guide plate is provided with light-guiding dots disposed on a bottom surface thereof. A light-shielding layer disposed on the light guide plate has a light-shielding portion and a light-transmitting portion corresponding to at least one of the key switches. The reflecting surface faces the bottom surface of the light guide plate, and a pattern at least partially overlaps the light-shielding portion. A first light-emitting device and a second light-emitting device are disposed in an opening of the light guide plate, and the first light-emitting device and the second light-emitting device face respective sidewalls of the opening. The first light-emitting device is located underneath the light-shielding portion.

Abstract: An infrared thermopile sensor includes a silicon cover having an infrared lens, an infrared sensing chip having duo-thermopile sensing elements, and a microcontroller chip calculating a temperature of an object. The components are in a stacked 3D package to decrease the size of the infrared thermopile sensor. The infrared sensing chip and the microcontroller chip have metal layers to shield the thermal radiation. The conversion from wrist temperature to body core temperature uses detected ambient temperature and fixed humidity or imported humidity level to calculate the body core temperature based on experimental data and curve fitting. The skin temperature compensation can be set differently for different sex gender, different standard deviation of wrist temperature and external relative humidity reading.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

Abstract: In a method of manufacturing a semiconductor device, a separation wall made of a dielectric material is formed between two fin structures. A dummy gate structure is formed over the separation wall and the two fin structures. An interlayer dielectric (ILD) layer is formed over the dummy gate structure. An upper portion of the ILD layer is removed, thereby exposing the dummy gate structure. The dummy gate structure is replaced with a metal gate structure. A planarization operation is performed to expose the separation wall, thereby dividing the metal gate structure into a first gate structure and a second gate structure. The first gate structure and the second gate structure are separated by the separation wall.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.

Abstract: A method for semiconductor manufacturing is provided. The method includes defining a first cell level group comprising a first set of pattern features corresponding to a predetermined manufacturing process associated with an layout; determining a first number of cell units based on the first cell level group, wherein each of the first number of cell units is compatible with each other; defining a second cell level group comprising the first set of pattern features and a second set of pattern features; and determining a second number of cell units based on the second cell level group, wherein each of the second number of cell units is compatible with each other. The first set of pattern features and the second set of pattern features are arranged in responsive to sequential operations of the predetermined manufacturing process.

Abstract: An integrated circuit is provided and includes first and second gates arranged in first and second layers, wherein the first and second gates extend in a first direction; a first insulating layer interposed between the first and second gates, wherein the first insulating layer, a first portion of the first gate, and a first portion of the second gate overlap with each other in a layout view; a cut layer, different from the first insulating layer, disposed on a second portion of the first gate; a first via passing through the cut layer and coupled to the second portion of the first gate; and a second via overlapping the first portion of the first gate and the first portion of the second gate, and coupled to the second gate. The first and second vias are configured to transmit different control signals to the first and second gates.

Abstract: An inductor and a power module are respectively provided. The inductor includes an insulating body and a conductive body. The insulating body has a top surface and a bottom surface. The conductive body includes two pin parts and a heat dissipation part. A portion of each of the pin parts is exposed outside the bottom surface. The portions of the two pin parts exposed outside the insulating body are configured to fix to a circuit board. The heat dissipation part is connected to the two pin parts, the heat dissipation part is exposed outside the top surface, and the heat dissipation part is configured to connect to an external heat dissipation member. When the inductor is fixed to the circuit board through the two pin parts exposed outside the bottom surface, the two pin parts and the bottom surface jointly define an accommodating space for accommodating a chip.

Abstract: A method (of manufacturing conductors for a semiconductor device) includes: forming active regions (ARs) in a first layer, the ARs extending in a first direction; forming a conductive layer over the first layer; forming first, second and third caps over the conductive layer, the caps extending in a second direction perpendicular to the first direction, and the caps having corresponding first, second and third sensitivities that are different from each other; removing portions of the conductive layer not under the first, second or third caps resulting in gate electrodes under the first caps and first and second drain/source (D/S) electrodes correspondingly under the second or third caps; and selectively removing portions of corresponding ones of the first D/S electrodes and the second D/S electrodes.

Abstract: A connecting structure includes a case, a rotating shaft, and a cable organizer. The case includes a hollow shell and an assembly plate. The assembly plate is accommodated in the hollow shell, and two through holes are formed between two opposite side edges of the assembly plate and an inner wall of the hollow shell. The rotating shaft is assembled to one side of the assembly plate. The cable organizer includes a tubular body, a spacer, and two inserts. The spacer is located at one end of the tubular body, and the two inserts are located at two opposite sides of another end of the tubular body. When the cable organizer is assembled to the case from the other side of the assembly plate, the two inserts respectively penetrate through the two through holes and are engaged with and fixed to the inner wall of the hollow shell.

Abstract: A semiconductor device including a first oxide definition (OD) strip doped by a first-type dopant in a first doping region defining an active region of a first Metal-Oxide Semiconductor (MOS); a second OD strip doped by a second-type dopant in a second doping region and a third doping region, the second doping region defining an active region of a second MOS and the third doping region defining a body terminal of the first MOS, wherein the second OD is parallel to the first OD strip; and a first dummy OD strip, wherein a boundary between the second doping region and the third doping region is formed over the first dummy OD strip; wherein the first-type dopant is different from the second-type dopant.

Abstract: A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

Abstract: An augmented reality implementing method applied to a server, which includes a plurality of augmented reality objects and a plurality of setting records corresponding to the augmented reality objects respectively is provided. Firstly, the server receives an augmented reality request from a mobile device, where the augmented reality request is related to a target device. Then, the server is communicated with the target device to access current information. Then, the server determines the current information corresponds to which one of the setting records, and selects one of the augmented reality objects based on the determined setting record as a virtual object provided to the mobile device.