Abstract: A method of fabricating an integrated circuit. The method includes generating two first-type active zones and two second-type active zones, and generating a gate-strip intersecting the two first-type active zones and the two second-type active zones. The method further includes patterning one or more poly cuts intersecting the gate-strip based on a determination of a difference between the poly extension effect of a p-type transistor and the poly extension effect of an n-type transistor.

Abstract: A semiconductor cell structure includes first-type transistors aligned within a first-type active zone, second-type transistors aligned within a second-type active zone, a first power rail and a second power rail. Each of the first-type active zone and the second-type active zone is between a first alignment boundary and a second alignment boundary extending in a first direction which is perpendicular to a second direction. A first distance along the second direction between the long edge of the first power rail and the first alignment boundary of the first-type active zone is different from a second distance along the second direction between the long edge of the second power rail and the first alignment boundary of the second-type active zone by a predetermined distance.

Abstract: An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of fin structures extending in a first direction over a semiconductor substrate. Each fin structure includes a first region proximate to the semiconductor substrate and a second region distal to the semiconductor substrate. An electrically conductive layer is formed between the first regions of a first adjacent pair of fin structures. A gate electrode structure is formed extending in a second direction substantially perpendicular to the first direction over the fin structure second region, and a metallization layer including at least one conductive line is formed over the gate electrode structure.

Abstract: A method includes fabricating semiconductor structures extending in a first direction and fabricating gate-conductors extending in a second direction intersecting the semiconductor structure. The method also includes patterning a first metal layer to form horizontal conducting lines extending in the first direction, and patterning the second metal layer to form vertical conducting lines extending in the second direction. A first vertical conducting line is aligned with a first gate-conductor underneath and a second vertical conducting line is aligned with a vertical boundary of a circuit cell. The first vertical conducting line is directly connected to a first horizontal conducting line through a first pin-connector, and the second vertical conducting line is directly connected to a second horizontal conducting line through a second pin-connector.

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.

Abstract: Methods and Apparatuses for making an integrated circuit (IC) are disclosed. In accordance with some embodiments, a method including forming one or more decoupling capacitor (DCAP) cells comprising one or more polysilicon (PO) layers openings formed based on one or more photoresist layer openings formed to solve one or more design rule check (DRC) violations. The one or more DCAP cells also provide decoupling capacitors for the IC.

Abstract: An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

Abstract: A method includes forming a first transistor stack over a substrate. The first transistor stack includes: a first transistor of a first conductivity type, and a second transistor of a second conductivity type different from the first conductivity type. The second transistor is above the first transistor. A plurality of first conductive lines is formed in a first metal layer above the first transistor stack. The plurality of first conductive lines includes, over the first transistor stack, a power conductive line configured to route power to the first transistor stack, one or more signal conductive lines configured to route one or more signals to the first transistor stack, and a shielding conductive line configured to shield the routed one or more signals. The one or more signal conductive lines are between the power conductive line and the shielding conductive line.

Abstract: An integrated circuit (IC) structure includes first and second active areas extending in a first direction in a semiconductor substrate, first and second gate structures extending in a second direction perpendicular to the first direction, wherein each of the first and second gate structures overlies each of the first and second active areas, a first metal-like defined (MD) segment extending in the second direction between the first and second gate structures and overlying each of the first and second active areas, and an isolation structure positioned between the first MD segment and the first active area. The first MD segment is electrically connected to the second active area and electrically isolated from a portion of the first active area between the first and second gate structures.

Abstract: A semiconductor device includes a semiconductor substrate with active regions and a first buried metal layer provided below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail, a first set of buried conductive fingers that extends from the first buried conductive rail, and a second set of buried conductive fingers that are interleaved with the first set of buried conductive fingers. The first set and the second set of buried conductive fingers extends beneath more than one of the active regions. In this manner, the first set and the second set of buried conductive fingers can be utilized to distribute different voltages, such as an ungated reference voltage TVDD and a gated reference voltage VVDD in a header circuit with reduced resistance.

Abstract: A semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a first source/drain structure and a second source/drain structure of a first transistor. The semiconductor device includes a third source/drain structure and a fourth source/drain structure of a second transistor. The second source/drain structure and the third source/drain structure merges as a common source/drain structure. The semiconductor device includes a first interconnect structure extending along a first lateral direction and disposed above the common source/drain structure. The semiconductor device includes a first dielectric structure interposed between the first interconnect structure and the common source/drain structure.

Abstract: A cell on an integrated circuit is provided. The cell includes: a fin structure; an intermediate fin structure connection metal track disposed in an intermediate fin structure connection metal layer above the fin structure, the intermediate fin structure connection metal track being connected to the fin structure; and a first intermediate gate connection metal track disposed in an intermediate gate connection metal layer above the intermediate fin structure connection metal layer, the first intermediate gate connection metal track being connected to the intermediate fin structure connection metal track. A first power supply terminal is connected to the first intermediate gate connection metal track.

Abstract: An integrated circuit includes a set of active regions, a first contact, a set of gates, a first and second conductive line and a first and second via. The set of active regions extends in a first direction, and is on a first level. The first contact extends in a second direction, is on a second level, and overlaps at least a first active region. The set of gates extends in the second direction, overlaps the set of active regions, and is on a third level. The first conductive line and the second conductive line extend in the first direction, overlap the first contact, and are on a fourth level. The first via electrically couples the first contact and the first conductive line together. The second via electrically couples the first contact and the second conductive line together.

Abstract: An integrated circuit device includes a first-type transistor having a channel region in a first-type active-region semiconductor structure and a second-type transistor having a channel region in a second-type active-region semiconductor structure which is stacked with the first-type active-region semiconductor structure. In the integrated circuit, a front-side power rail and a front-side signal line in a front-side conductive layer extend in the first direction is, and a back-side power rail and a back-side signal line in a back-side conductive layer also extend in the first direction. The front-side conductive layer is above the first-type active-region semiconductor structure and the second-type active-region semiconductor structure, while the back-side conductive layer is below the first-type active-region semiconductor structure and the second-type active-region semiconductor structure.

Abstract: An integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor includes a first active area extending in a first direction in a first layer. The second transistor includes a second active area that is disposed in a second layer below the first layer and overlaps the first active area. The third transistor includes at least two third active areas extending in the first direction in the first layer. In the first direction, a boundary line of one of the at least two third active areas is aligned with boundary lines of the first and second active areas. The fourth transistor includes at least two fourth active areas that are disposed in the second layer and overlap the at least two third active areas.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.

Abstract: A manufacturing method of an input circuit of a flip-flop including: depositing a first gate strip, a second gate strip, a third gate strip, and a fourth gate strip, wherein a distance between the first and second gate strips, a distance between the second and third gate strips, and a distance between the third and fourth gate strips equal; executing a cut-off operation upon the first gate strip to generate a first first gate strip and a second first gate strip; executing a cut-off operation upon the third gate strip to generate a first third gate strip and a second third gate strip; and directing a first signal to the first first gate strip and the second third gate strip, and a second signal to the second first gate strip and the first third gate strip.