Patents by Inventor Chih Liang

Chih Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ELECTRONIC DEVICE
    Publication number: 20230244586
    Abstract: The disclosure provides an electronic device. The electronic device includes a computer system, a light emitting module, and a control unit. The computer system is adapted to execute a boot procedure, the boot procedure lasting for a first time period. A light emitting module includes a plurality of indicator lights, each indicator light providing an indication function. The control unit is electrically connected to the light emitting module. The control unit controls the indicator lights to generate a first light emitting effect within a second time period when the computer system enters the boot procedure. The second time period is shorter than the first time period.
    Type: Application
    Filed: September 20, 2022
    Publication date: August 3, 2023
    Inventors: Fu-Yu CAI, Chun-Fu CHEN, Che-Hsiung CHAO, Ming-Chih HUANG, Tong-Shen HSIUNG, Shang-Chih LIANG
  • METHOD OF MAKING SEMICONDUCTOR DEVICE WHICH INCLUDES FINS
    Publication number: 20230247817
    Abstract: A method (of manufacturing fins for a semiconductor device) includes: forming semiconductor fins including ones thereof having a first cap with a first etch sensitivity (first capped fins) and second ones thereof having a second cap with a second etch sensitivity (second capped fins), the first and second etch sensitivities being different; and eliminating selected ones of the first capped fins and selected ones of the second capped fins.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 3, 2023
    Inventors: Chih-Liang CHEN, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Chin-Yuan TSENG, Jiann-Tyng TZENG, Kam-Tou SIO, Ru-Gun LIU, Wei-Liang LIN, L. C. CHOU
  • Method and system for packet processing according to a table lookup
    Patent number: 11711305
    Abstract: The present invention provides a method for packet processing according to a lookup table, comprising: receiving a packet, wherein the packet includes a packet header, and the packet header consists of control information; providing a lookup table with M entries, wherein each entry includes N conditions and a result/action indicator, and the M entries are sorted in a priority order; matching the information with the N conditions; and applying the result/action indicator in the matched entry with the highest priority on the packet.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: July 25, 2023
    Inventors: Yi-Lung Hsiao, Chih-Liang Chou
  • Method of making standard cells having via rail and deep via structures
    Patent number: 11688691
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to forming via rail and deep via structures to reduce parasitic capacitances in standard cell structures. Via rail structures are formed in a level different from the conductive lines. The via rail structure can reduce the number of conductive lines and provide larger separations between conductive lines that are on the same interconnect level and thus reduce parasitic capacitance between conductive lines.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: June 27, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Cheng Lin, Cheng-Chi Chuang, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Ting Yang, Wayne Lai
  • Method and system of manufacturing conductors and semiconductor device which includes conductors
    Patent number: 11688730
    Abstract: A system that generates a layout diagram has a processor that implements a method, the method including: generating first and second conductor shapes; generating first, second and third cap shapes correspondingly over the first and second conductor shapes; arranging a corresponding one of the second conductor shapes to be interspersed between each pair of neighboring ones of the first conductor shapes; generating first cut patterns over selected portions of corresponding ones of the first cap shapes; and generating second cut patterns over selected portions of corresponding ones of the second cap shapes. In some circumstances, the first cut patterns are designated as selective for a first etch sensitivity corresponding to the first cap shapes; and the second cut patterns are designated as selective for a second etch sensitivity corresponding to the second cap shapes.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Hui-Ting Yang, Shun Li Chen, Ko-Bin Kao, Chih-Ming Lai, Ru-Gun Liu, Charles Chew-Yuen Young
  • SEMICONDUCTOR DEVICE INCLUDING SOURCE/DRAIN CONTACT HAVING HEIGHT BELOW GATE STACK
    Publication number: 20230187434
    Abstract: A method is provided, including the following operations: arranging a first gate structure extending continuously above a first active region and a second active region of a substrate; arranging a first separation spacer disposed on the first gate structure to isolate an electronic signal transmitted through a first gate via and a second gate via that are disposed on the first gate structure, wherein the first gate via and the second gate via are arranged above the first active region and the second active region respectively; and arranging a first local interconnect between the first active region and the second active region, wherein the first local interconnect is electrically coupled to a first contact disposed on the first active region and a second contact disposed on the second active region.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Charles Chew-Yuen YOUNG, Chih-Liang CHEN, Chih-Ming LAI, Jiann-Tyng TZENG, Shun-Li CHEN, Kam-Tou SIO, Shih-Wei PENG, Chun-Kuang CHEN, Ru-Gun LIU
  • Integrated circuit and method for forming the same
    Patent number: 11676896
    Abstract: A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Liang Chen, Li-Chun Tien
  • Semiconductor device and method of manufacturing the same
    Patent number: 11664380
    Abstract: A semiconductor device having a standard cell, includes a first power supply line, a second power supply line, a first gate-all-around field effect transistor (GAA FET) disposed over a substrate, and a second GAA FET disposed above the first GAA FET. The first power supply line and the second power supply line are located at vertically different levels from each other.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 30, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guo-Huei Wu, Jerry Chang Jui Kao, Chih-Liang Chen, Hui-Zhong Zhuang, Jung-Chan Yang, Lee-Chung Lu, Xiangdong Chen
  • NON-TRANSITORY COMPUTER-READABLE MEDIUM, INTEGRATED CIRCUIT DEVICE AND METHOD
    Publication number: 20230154917
    Abstract: A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.
    Type: Application
    Filed: January 19, 2023
    Publication date: May 18, 2023
    Inventors: Chih-Liang CHEN, Shun Li CHEN, Li-Chun TIEN, Ting Yu CHEN, Hui-Zhong ZHUANG
  • ARRANGEMENT OF SOURCE OR DRAIN CONDUCTORS OF TRANSISTOR
    Publication number: 20230154990
    Abstract: An integrated circuit includes a first conductor segment intersecting a first active-region structure at a source/drain region and a second conductor segment intersecting a second active-region structure at a source/drain region. The first conductor segment and the second conductor segment are separated at proximal edges by a separation distance. The first conductor has a distal edge separated from a first power rail, and the second conductor segment is connected to a second power rail through a via-connector. A distance from the first power rail to a proximal edge of the first conductor segment is larger than a distance from the second power rail to a proximal edge of the second conductor segment by a predetermined distance that is a fraction of the separation distance.
    Type: Application
    Filed: November 12, 2021
    Publication date: May 18, 2023
    Inventors: Chih-Yu LAI, Chih-Liang CHEN, Chi-Yu LU, Shang-Hsuan CHIU
  • Integrated circuit structure and method of forming the same
    Patent number: 11652102
    Abstract: An integrated circuit structure includes a first well, a second well, a third well, a first set of implants and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion of the first well, extending in the first direction and having a second width. The second well has a second dopant type and is adjacent to the first well. The third well has the second dopant type, and is adjacent to the first well. The first portion of the first well is between the second well and the third well. The first set of implants is in the first portion of the first well, the second well and the third well. The second set of implants is in the second portion of the first well.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu
  • KEYBOARD BACKLIGHT MODULE AND APPLICATIONS THEREOF
    Publication number: 20230138295
    Abstract: A backlit keyboard includes key switches and a backlight module. The backlight module includes a light guide plate, a reflecting surface, and at least one light-emitting device. The light guide plate is provided with light-guiding dots disposed on a bottom surface thereof. A light-shielding layer disposed on the light guide plate has a light-shielding portion and a light-transmitting portion corresponding to at least one of the key switches. The reflecting surface faces the bottom surface of the light guide plate, and a pattern at least partially overlaps the light-shielding portion. A first light-emitting device and a second light-emitting device are disposed in an opening of the light guide plate, and the first light-emitting device and the second light-emitting device face respective sidewalls of the opening. The first light-emitting device is located underneath the light-shielding portion.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 4, 2023
    Inventor: Hsin-Chih LIANG
  • MULTI-PHASE INDUCTOR STRUCTURE
    Publication number: 20230131138
    Abstract: A multi-phase inductor structure is provided. The multi-phase inductor structure includes a first magnetic core, two second magnetic cores, and two first electrical conductors. The two second magnetic cores are respectively arranged on opposite sides of the first magnetic core, and each have a first engagement surface. A first annular convex wall and a first upright convex wall are formed on the first engagement surface, and a first recess is formed therebetween. The two first electrical conductors are respectively arranged in two of the first recesses of the first engagement surface, and each have has a first body and two first pins that are respectively connected to two ends of the first body. The two first pins extend in opposite directions. A magnetic permeability of the first magnetic core is different from a magnetic permeability of each of the two second magnetic cores.
    Type: Application
    Filed: March 14, 2022
    Publication date: April 27, 2023
    Inventors: HUNG-CHIH LIANG, PIN-YU CHEN, HSIU-FA YEH, HANG-CHUN LU, YA-WAN YANG, YU-TING HSU, WEI-ZHI HUANG
  • SEMICONDUCTOR DEVICES, SEMICONDUCTOR STRUCTURES AND METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE
    Publication number: 20230127579
    Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.
    Type: Application
    Filed: May 30, 2022
    Publication date: April 27, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung CHEN, Szu-Lin LIU, Jaw-Juinn HORNG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Ya Yun LIU
  • Advanced metal connection with metal cut
    Patent number: 11637064
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 25, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Semiconductor device with V2V rail and methods of making same
    Patent number: 11637069
    Abstract: A semiconductor device including: an active region; first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction and correspondingly overlap the active region; a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, and overlaps the first, second and third MD contact structures; a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and, relative to the second direction, overlaps each of the first, second and third MD contact structures; and a first via-to-MD (VD) structure between the first MD contact structure and the first conductive segment, the first VD structure electrically coupling the first conductive segment, the V2V rail and the first MD contact structure; wherein at least one of the second or third MD contact structures is electrically decoupled from the V2V rail.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: April 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jung-Chan Yang, Chi-Yu Lu, Hui-Zhong Zhuang, Chih-Liang Chen
  • INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME
    Publication number: 20230124119
    Abstract: An integrated circuit includes a gated circuit configured to operate on a first or second voltage, a header circuit, a first power rail and a second power rail on a back-side of a wafer, a third power rail on the back-side of the wafer, and a fourth power rail on a front-side of the wafer. The first and second power rail extend in a first direction, and are separated from each other in a second direction. The third power rail is between the first and second power rail in the second direction. The third power rail is configured to supply the second voltage to the gated circuit. The fourth power rail includes a first set of conductors extending in the second direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit, and is separated from each other in the first direction.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Kuang-Ching CHANG, Jung-Chan YANG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Kuo-Nan YANG
  • MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL
    Publication number: 20230113294
    Abstract: A method includes: disposing a first conductive segment; disposing a first conductive via above the first conductive segment; disposing a first conductive line above the first conductive via; and disposing a second conductive segment electrically coupled to the first conductive line through a third conductive segment, the first conductive segment, and the first conductive via.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 13, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN
  • INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME
    Publication number: 20230114558
    Abstract: An integrated circuit includes a first power rail, a conductive structure, a first active region of a first set of transistors and a second active region of a second set of transistors. The first power rail is on a back-side of a substrate, extends in a first direction, and is configured to supply a first supply voltage. The first active region extends in the first direction, and is on a first level of a front-side of the substrate opposite from the back-side. The second active region extends in the first direction, is on the first level of the front-side of the substrate, and is separated from the first active region in a second direction different from the first direction. The conductive structure is on the back-side of the substrate, extends in the first direction, and is electrically coupled to the first active region and the second active region.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Inventors: Guo-Huei WU, Pochun WANG, Wei-Hsin TSAI, Chih-Liang CHEN, Li-Chun TIEN
  • MIDDLE-END-OF-LINE STRAP FOR STANDARD CELL
    Publication number: 20230103578
    Abstract: A semiconductor structure includes a first conductive line, a first conductive segment, a second conductive segment, and a third conductive segment. The first conductive segment is electrically coupled to the first conductive line. The second conductive segment is electrically coupled the first conductive segment. The second conductive segment is disposed between the first conductive segment and the third conductive segment. A top surface of the first conductive segment is aligned with a top surface of the second conductive segment in a same layer.
    Type: Application
    Filed: December 12, 2022
    Publication date: April 6, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hung SHEN, Chih-Liang CHEN, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Kam-Tou SIO, Wei-Cheng LIN