Abstract: A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength ?; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.

Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.

Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.

Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.

Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,

Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.

Abstract: An integrated circuit (IC) device has a memory region in which a plurality of memory cells is implemented. Each of the memory cells has a first dimension in a first horizontal direction. The IC device includes an edge region bordering the memory cell region in the first horizontal direction. The edge region has a second dimension in the first horizontal direction. The second dimension is less than or equal to about 4 times the first dimension. The IC device is formed by revising a first IC layout to generate a second IC layout. The second IC layout is generated by shrinking a dimension of the edge region in the first horizontal direction.

Abstract: A method for processing a curved plastic panel is to first form a hard coating layer, an optical function layer, and a printing layer on a flat plastic substrate, and then cut it into a predetermined shape, and then use a hot pressing and curving device to perform a hot pressing and curving process to the flat plastic substrate in order to make it becoming a curved plastic substrate. The hot pressing and curving device can simultaneously perform hot pressing during the heating process, and has the functions of real-time monitoring of the local temperature and the local curvature forming state, and then feedback to the local heating and curvature forming mechanism for adjustments. The monitoring of temperature and curvature can be divided into multiple stages, which can be monitored stage by stage and adjusted for heating or curvature forming to improve production yield.

Abstract: A method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack comprising alternative first and second semiconductor layers over a semiconductor substrate; patterning the epitaxial stack to form first and second semiconductor fins; removing the first semiconductor layers in the first and second semiconductor fins, while leaving a first set of the second semiconductor layers in the first semiconductor fin and a second set of the second semiconductor layers in the second semiconductor fin; forming a gate dielectric layer around the first and second sets of the second semiconductor layers; depositing a gate metal layer over the gate dielectric layer; etching a recess in the gate metal layer and between the first and second sets of the second semiconductor layers, wherein the gate metal layer has a first portion below the recess; and forming a dielectric feature in the recess.

Abstract: A light-guide sunroof assembly comprises a plastic substrate and a light source module furnished besides the plastic substrate. An outer layer of the plastic substrate is added with dye to form a colored background. A plurality of light-guide microstructures is furnished on the plastic substrate to guide the light generated by the light source module toward an inner surface of the plastic substrate. Thereby, the light generated by the light source module is guided by the plastic substrate and then ejects out of the inner surface of plastic substrate, so as to provide a light decoration or lighting effect that enriches the visual experience. Moreover, the plastic substrate is first formed into a curved plastic plate through a hot pressing process, and then a connecting structure is formed and fixed on the plastic plate by an insert-molding injection process, in order to replace the traditional car sunroof mechanism which is assembled by glass plate bonded with metal connecting parts.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

Abstract: The present disclosure provides a voltage monitor and a semiconductor device including the voltage monitor. The voltage monitor includes a first voltage-to-digital converter (VDC), a second VDC, a first digital-to-binary converter (DBC), a second DBC, and an adder. The first VDC is configured to generate a first digital signal in response to a clock signal, and the second VDC is configured to generate a second digital signal in response to the clock signal. The first DBC is connected to the first VDC, and configured to convert the first digital signal to a first binary signal. The second DBC is connected to the second VDC, and configured to convert the second digital signal to a second binary signal. The adder is connected to the first DBC and the second DBC, and configured to combine the first binary signal and the second binary signal into an output signal.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.

Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.

Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.

Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.

Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.