Patents by Inventor Chih-Lin Chen
Chih-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250120166Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
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Publication number: 20250120115Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate structure disposed over and interleaved with the stack of semiconductor layers, the metal gate structure including a gate electrode disposed over a gate dielectric layer, a first isolation structure disposed adjacent to a first sidewall of the stack of semiconductor layers, where the gate dielectric layer fills space between the first isolation structure and the first sidewall of the stack of semiconductor layers, and a second isolation structure disposed adjacent to a second sidewall of the stack of semiconductor layers, where the gate electrode fills the space between the second isolation structure and the second sidewall of the stack of semiconductor layers.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Inventors: Shi Ning Ju, Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
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Patent number: 12269405Abstract: A multiple detection system is applied to a vehicle and includes a contact-type detection module adapted to generate a contact-type detection datum, a contactless-type detection module adapted to generate a contactless-type detection datum, and an operation processor electrically connected with the contact-type detection module and the contactless-type detection module in a wire manner or in a wireless manner. The operation processor sets at least one of the contact-type detection datum and the contactless-type detection datum according to an environmental status of the vehicle to be a main detection result of the multiple detection system, and further sets the other detection datum to be an auxiliary detection result of the multiple detection system, for acquiring a passenger feature inside the vehicle.Type: GrantFiled: November 26, 2020Date of Patent: April 8, 2025Assignee: PixArt Imaging Inc.Inventors: Han-Lin Chiang, Shih-Feng Chen, Yen-Min Chang, Ning Shyu, Chih-Wei Huang
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Publication number: 20250113539Abstract: A method includes forming semiconductive sheets over a substrate and arranged in a vertical direction; forming source/drain regions on either side of each of the semiconductive sheets; forming first air gap inner spacers interleaving with the semiconductive sheets; forming a gate around each of the semiconductive sheets, wherein the first air gap inner spacers are laterally between the gate and a first one of the source/drain regions.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250109847Abstract: A connecting device used for electrically connecting a power source with a power consuming module is provided. The connecting device includes a female connecting base and a male connecting base. The female connecting base has two opposite surfaces, a rim disposed on one of the surfaces and two terminals exposed on the surfaces. The terminals are connected to the live wire and neutral wire of the power source separately. The male connecting base includes a clamp, two conductive strips, and a ground strip. The rim is clamped, and the male connecting base is fastened to the female connecting base by the clamp. The terminals are connected to the conductive strips, while the end surface of each conductive strip protrudes from the surface of the male connecting base. The ground strip includes a ground surface which protrudes from the end surfaces of the conductive strips.Type: ApplicationFiled: May 16, 2024Publication date: April 3, 2025Inventors: Chih-Hung JU, Chung-Kuang CHEN, Yi-An LIN, Guo-Hao HUANG, Pin-Tsung WANG
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Patent number: 12265295Abstract: An electronic device includes pixel regions and pixel spacing regions, and includes: a display layer disposed in the pixel regions and the pixel spacing regions, and including a liquid crystal material and a dye material; and reflective layers respectively disposed in the pixel regions, and at one side of the display layer. The display layer is in a scattering state under a non-display state, and light is scattered by the liquid crystal material and absorbed by the dye material when the light passes through the display layer. The display layer in the pixel regions is in a transmissive state and the display layer in the pixel spacing regions is in a scattering state under a display state, and light passes through the liquid crystal material and the dye material in the pixel regions and is reflected by the reflective layers when the light passes through the display layer.Type: GrantFiled: February 22, 2024Date of Patent: April 1, 2025Assignee: INNOLUX CORPORATIONInventors: Hsu-Kuan Hsu, Tzu-Chieh Lai, Chih-Chin Kuo, En-Hsiang Chen, Wenqi Lin, Mao-Shiang Lin
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Patent number: 12266704Abstract: Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. The methods described herein allow for complex shapes (e.g., “L-shaped”) to be etched into a multi-layered stack to form fins used in the formation of active regions of the GAA nanostructure transistor structures. In some embodiments, the active regions may be formed with a first channel width and a first source/drain region having a first width and a second channel width and a second source/drain region having a second width that is less than the first width.Type: GrantFiled: May 26, 2023Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning Ju, Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20250104191Abstract: A detecting system includes a camera and a processor. The camera is configured to capture a first target object to generate a first image and is configured to capture a second target object different from the first target object to generate a second image. The processor is configured to detect the first image by using a first model to generate a first result and is configured to train the first model by using the first result. When the processor trains the first model by using the first result, the camera captures the second target object. After the camera captures the second target object, the processor further trains the first model by using the second image.Type: ApplicationFiled: December 15, 2023Publication date: March 27, 2025Inventors: Gan-Lin CHEN, Chun-Lin CHIEN, Chih-Chung CHIU, Chih-Ping HO
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Patent number: 12262479Abstract: The present invention relates to an extension structure of flexible substrates with conductive wires thereon. In a first embodiment, three flexible substrates are prepared, each having multiple conductive wires configured on their front surfaces. The third flexible substrate is flipped over, with its conductive wires facing downwards, and bonded across a boundary formed by the first and second flexible substrates. As a result, the corresponding conductive wires between the first and second flexible substrates are electrically coupled with each other through being physically pressed by corresponding conductive wires in the third flexible substrate.Type: GrantFiled: March 16, 2023Date of Patent: March 25, 2025Assignee: UNEO INC.Inventors: Chih-Sheng Hou, Chia-Hung Chou, Hsin-Lin Yu, Si-Wei Chen, Chueh Chiang
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Publication number: 20250098293Abstract: A first gate-all-around (GAA) transistor and a second GAA transistor may be formed on a substrate. The first GAA transistor includes at least one silicon plate, a first gate structure, a first source region, and a first drain region. The second GAA transistor includes at least one silicon-germanium plate, a second gate structure, a second source region, and a second drain region. The first GAA transistor may be an n-type field effect transistor, and the second GAA transistor may be a p-type field effect transistor. The gate electrodes of the first gate structure and the second gate structure may include a same conductive material. Each silicon plate and each silicon-germanium plate may be single crystalline and may have a same crystallographic orientation for each Miller index.Type: ApplicationFiled: December 6, 2024Publication date: March 20, 2025Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG, Kuan-Lun CHENG, Guan-Lin CHEN
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Patent number: 12253506Abstract: A method of building upstream-and-downstream configuration of sensors includes determining two sets of geographic position data of a target sensor and a candidate sensor, obtaining pollution-associated periods according to pieces of flow field data, the sets of geographic position data and pieces of target sensing data of the target sensor to determine a pollution-associated period, calculating a correlation between target sensing data obtained by the target sensor during the pollution-associated period and candidate sensing data obtained by the candidate sensor during the associated air pollution period to obtain sensor correlations, and determining the target sensor and the candidate sensor having a upstream-and-downstream relationship with the candidate sensor being used as a satellite sensor of the target sensor when a quantity ratio of sensor correlations being larger than or equal to a correlation threshold is larger than or equal to a default ratio.Type: GrantFiled: October 19, 2022Date of Patent: March 18, 2025Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Lin Wang, Guang-Huei Gu, Chih-Jen Chen
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Publication number: 20250089348Abstract: A semiconductor device includes a bipolar junction transistor (BJT) structure including emitters in a first well having a first conductive type, collectors in respective second wells, the second wells having a second conductive type different from the first conductive type and being spaced apart from each other with the first well therebetween, and bases in the first well and between the emitters and the collectors. The BJT structure includes active regions having different widths that form the emitters, the collectors, and the bases.Type: ApplicationFiled: November 21, 2024Publication date: March 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chung CHEN, Szu-Lin LIU, Jaw-Juinn HORNG, Hui-Zhong ZHUANG, Chih-Liang CHEN, Ya Yun LIU
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Patent number: 12249621Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and first channel structures and second channel structures formed over the substrate. The semiconductor structure also includes a dielectric fin structure formed between the first channel structures and the second channel structures. In addition, the dielectric fin structure includes a core portion and first connecting portions connected to the core portion. The semiconductor structure also includes a gate structure including a first portion. In addition, the first portion of the gate structure is formed around the first channel structures and covers the first connecting portions of the dielectric fin structure.Type: GrantFiled: February 23, 2022Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Guan-Lin Chen, Jung-Chien Cheng, Kuo-Cheng Chiang, Shi-Ning Ju, Chih-Hao Wang
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Publication number: 20250081730Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.Type: ApplicationFiled: June 26, 2024Publication date: March 6, 2025Inventors: Andrew Lin, Alper Ozgurluk, Chao Liang Chien, Cheuk Chi Lo, Chia-Yu Chen, Chien-Chung Wang, Chih Pang Chang, Chih-Hung Yu, Chih-Wei Chang, Chin Wei Hsu, ChinWei Hu, Chun-Kai Tzeng, Chun-Ming Tang, Chun-Yao Huang, Hung-Che Ting, Jung Yen Huang, Lungpao Hsin, Shih Chang Chang, Tien-Pei Chou, Wen Sheng Lo, Yu-Wen Liu, Yung Da Lai
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Publication number: 20250079414Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.Type: ApplicationFiled: January 16, 2024Publication date: March 6, 2025Inventors: KUO-HSIEN LIAO, LI-CHENG SHEN, HUNG-YI TSAI, CHAO-HSUAN WANG, CHUN-MING CHEN, TAI-LIN WU, CHIH-SHIEN CHEN, PING-CHI HUNG
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Patent number: 12243966Abstract: A light-emitting device comprises a semiconductor stack emitting a light with a peak wavelength ?; and a light field adjustment layer formed on the semiconductor stack, wherein the light field adjustment layer comprises a plurality of first layers and a plurality of second layers alternately stacked on top of each other, the plurality of first layers each comprises a first optical thickness, and the plurality of second layers each comprises a second optical thickness.Type: GrantFiled: June 22, 2021Date of Patent: March 4, 2025Assignee: EPISTAR CORPORATIONInventors: Heng-Ying Cho, Li-Yu Shen, Chih-Hao Chen, Keng-Lin Chuang
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Publication number: 20250072052Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.Type: ApplicationFiled: January 11, 2024Publication date: February 27, 2025Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250069881Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.Type: ApplicationFiled: November 7, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
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Publication number: 20250062194Abstract: A semiconductor device includes a first conductive layer, a second conductive layer, a third conductive layer, a first organic layer, a first inorganic layer and a first silicon-containing layer. The third conductive layer is disposed between and electrically isolated from the first conductive layer and the second conductive layer. The first organic layer continuously covers the first conductive layer and the third conductive layer. The first inorganic layer is disposed over the first organic layer. The first silicon-containing layer is inserted between the first organic layer and the first inorganic layer, wherein the second conductive layer is disposed on and disposed in the first organic layer, the first silicon-containing layer and the first inorganic layer, to electrically connect to the first conductive layer.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Lung Yang, Chih-Hung Su, Chen-Shien Chen, Hon-Lin Huang, Kun-Ming Tsai, Wei-Je Lin
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Patent number: 12230744Abstract: A light-emitting device includes a substrate including a top surface, a first side surface and a second side surface, wherein the first side surface and the second side surface of the substrate are respectively connected to two opposite sides of the top surface of the substrate; a semiconductor stack formed on the top surface of the substrate, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a first electrode pad formed adjacent to a first edge of the light-emitting device; and a second electrode pad formed adjacent to a second edge of the light-emitting device, wherein in a top view of the light-emitting device, the first edge and the second edge are formed on different sides or opposite sides of the light-emitting device, the first semiconductor layer adjacent to the first edge includes a first sidewall directly connected to the first side surface of the substrate,Type: GrantFiled: September 20, 2023Date of Patent: February 18, 2025Assignee: EPISTAR CORPORATIONInventors: Chao-Hsing Chen, Cheng-Lin Lu, Chih-Hao Chen, Chi-Shiang Hsu, I-Lun Ma, Meng-Hsiang Hong, Hsin-Ying Wang, Kuo-Ching Hung, Yi-Hung Lin