Patents by Inventor Chih-Lin Chen
Chih-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145540Abstract: A semiconductor device includes a first active region, a second active region and a dielectric wall. The second active region disposed adjacent to the first active region, and there is a first space between the first active region and the second active region. The dielectric wall is formed within the first space and has a first sidewall and a second sidewall opposite to the first sidewall. The first sidewall and the second sidewall opposite to the first sidewall continuously extend along a plane.Type: ApplicationFiled: January 20, 2023Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shi Ning JU, Kuo-Cheng CHIANG, Guan-Lin CHEN, Jung-Chien CHENG, Chih-Hao WANG
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Publication number: 20240124706Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, and a fourth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), and the fourth repeating unit has a structure of Formula (IV), a structure of Formula (V) or a structure of Formula (VI) wherein A1, A2, A3, Z1, R1, R2, R3 and Q are as defined in the specification.Type: ApplicationFiled: September 22, 2023Publication date: April 18, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu-Lin CHU, Jen-Chun CHIU, Po- Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
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Patent number: 11942513Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.Type: GrantFiled: January 10, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang
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Patent number: 11942478Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.Type: GrantFiled: May 6, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Guan-Lin Chen
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Publication number: 20240096942Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Jung-Chien Cheng, Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Chih-Hao Wang, Kuan-Lun Cheng
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Publication number: 20240088001Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.Type: ApplicationFiled: September 19, 2023Publication date: March 14, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
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Publication number: 20240086633Abstract: A method for generating and outputting a message is implemented using an electronic device the stores a computer program product and a text database. The text database includes a main message template, a template text that includes a placeholder, and a word group that includes a plurality of preset words for replacing the placeholder. The method includes: in response to receipt of a command for execution of the computer program product, displaying an editing interface including the main message template; in response to receipt of user operation of a selection of the main message template, displaying the template text; in response to receipt of user operation of a selection of one of the preset words via the user interface, generating an edited text by replacing the placeholder with the one of the preset words in the template text; and outputting the edited text as a message.Type: ApplicationFiled: April 25, 2023Publication date: March 14, 2024Inventors: Yi-Ru CHIU, Ting-Yi LI, Hong-Xun WANG, Jin-Lin CHEN, Chih-Hsuan YEH, Chia-Chi YIN, Wei-Ting LI, Po-Lun CHANG
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Patent number: 11920778Abstract: A ventilation fan includes a housing having an opening, a grille structure positioned to cover the opening, a fan module provided in the housing and a function module. The grille structure includes a base defining an outlet, and a grille support spaced apart from the base and connected by the connecting columns A radial inlet is formed between the base and the grille support is in communication with the outlet. The base includes a holder having a holding opening axially downward and faced away from the housing. The function module is disposed within the holder through the holding opening.Type: GrantFiled: September 30, 2022Date of Patent: March 5, 2024Assignee: DELTA ELECTRONICS, INC.Inventors: Yu-Hsiang Huang, Yen-Lin Chen, Chih-Hua Lin
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Publication number: 20240065765Abstract: A method of orthopedic treatment includes steps of: by using a computer aided design (CAD) tool based on profile data that is related to a to-be-treated part of a bone of a patient, obtaining a model of a preliminary instrument that substantially fits the to-be-treated part; by using the CAD tool, obtaining a model of a patient specific instrument (PSI) based on the model of the preliminary instrument; producing the PSI based on the model of the PSI, the PSI being adjustable; performing medical operation on the to-be-treated part, and then attaching the PSI to the to-be-treated part; after attaching the PSI to the to-be-treated part, adjusting the PSI such that the PSI is adapted to real conditions of the to-be-treated part.Type: ApplicationFiled: August 22, 2023Publication date: February 29, 2024Inventors: Alvin Chao-Yu CHEN, Yi-Sheng CHAN, Chi-Pin HSU, Shang-Chih LIN, Chin-Ju WU, Jeng-Ywan JENG
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Publication number: 20230299052Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.Type: ApplicationFiled: May 23, 2023Publication date: September 21, 2023Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
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Patent number: 11658157Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.Type: GrantFiled: June 10, 2021Date of Patent: May 23, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Hui-Yu Lee, Fong-Yuan Chang, Po-Hsiang Huang, Chin-Chou Liu
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Patent number: 11562926Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.Type: GrantFiled: August 29, 2020Date of Patent: January 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin Chen, Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
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Publication number: 20210305213Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
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Patent number: 11075136Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.Type: GrantFiled: February 7, 2020Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
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Patent number: 11043473Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: GrantFiled: December 18, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
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Publication number: 20200402847Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.Type: ApplicationFiled: August 29, 2020Publication date: December 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
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Patent number: 10763164Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.Type: GrantFiled: November 17, 2016Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin Chen, Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
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Publication number: 20200176349Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.Type: ApplicationFiled: February 7, 2020Publication date: June 4, 2020Inventors: Ying-Chih HSU, Alan ROTH, Chuei-Tang WANG, Chih-Yuan CHANG, Eric SOENEN, Chih-Lin CHEN
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Publication number: 20200126952Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Chih-Lin CHEN, Chin-Chou LIU, Fong-Yuan CHANG, Hui-Yu LEE, Po-Hsiang HUANG
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Patent number: 10559517Abstract: An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.Type: GrantFiled: November 29, 2018Date of Patent: February 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen