Patents by Inventor Chih-Lin Chen
Chih-Lin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210305213Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by at least the through substrate via.Type: ApplicationFiled: June 10, 2021Publication date: September 30, 2021Inventors: Chih-Lin CHEN, Hui-Yu LEE, Fong-Yuan CHANG, Po-Hsiang HUANG, Chin-Chou LIU
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Patent number: 11075136Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.Type: GrantFiled: February 7, 2020Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
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Patent number: 11043473Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: GrantFiled: December 18, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
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Publication number: 20200402847Abstract: A method of forming a package structure includes: forming an inductor comprising a through-via over a carrier; placing a semiconductor device over the carrier; molding the semiconductor device and the through-via in a molding material; and forming a first redistribution layer on the molding material, wherein the inductor and the semiconductor device are electrically connected by the first redistribution layer.Type: ApplicationFiled: August 29, 2020Publication date: December 24, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
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Patent number: 10763164Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.Type: GrantFiled: November 17, 2016Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin Chen, Chung-Hao Tsai, Jeng-Shien Hsieh, Chuei-Tang Wang, Chen-Hua Yu, Chih-Yuan Chang
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Publication number: 20200176349Abstract: A method of transferring heat in a package includes conducting heat from a first device to a second device by a low thermal resistance substrate path in a chip layer of the package, conducting heat from an integrated circuit (IC) to a first package layer of the package, conducting heat from the first package layer of the package to at least a first set of through-vias positioned in the chip layer, and conducting heat from the first set of through-vias to a surface of a second package layer opposite the chip layer. The first device and the second device is part of the IC chip. The first package layer is adjacent to the chip layer.Type: ApplicationFiled: February 7, 2020Publication date: June 4, 2020Inventors: Ying-Chih HSU, Alan ROTH, Chuei-Tang WANG, Chih-Yuan CHANG, Eric SOENEN, Chih-Lin CHEN
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Publication number: 20200126952Abstract: An integrated circuit includes a first and second semiconductor wafer, a bonding layer, a first and second interconnect structure, an inductor, and a through substrate via. The first semiconductor wafer has a first device in a first side of the first semiconductor wafer. The second semiconductor wafer is over the first semiconductor wafer. The bonding layer is between the first and the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer. The inductor is below the first semiconductor wafer. At least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the first side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: ApplicationFiled: December 18, 2019Publication date: April 23, 2020Inventors: Chih-Lin CHEN, Chin-Chou LIU, Fong-Yuan CHANG, Hui-Yu LEE, Po-Hsiang HUANG
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Patent number: 10559517Abstract: An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.Type: GrantFiled: November 29, 2018Date of Patent: February 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
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Patent number: 10535635Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: GrantFiled: June 15, 2018Date of Patent: January 14, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Lin Chen, Chin-Chou Liu, Fong-Yuan Chang, Hui-Yu Lee, Po-Hsiang Huang
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Publication number: 20190385980Abstract: An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, an inductor, a second interconnect structure and a through substrate via. The first semiconductor wafer has a first device in a front side of the first semiconductor wafer. The second semiconductor wafer is bonded to the first semiconductor wafer. The first interconnect structure is below a backside of the first semiconductor wafer. The inductor is below the first semiconductor wafer, and at least a portion of the inductor is within the first interconnect structure. The second interconnect structure is on the front side of the first semiconductor wafer. The through substrate via extends through the first semiconductor wafer. The inductor is coupled to at least the first device by the second interconnect structure and the through substrate via.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: Chih-Lin CHEN, Chin-Chou LIU, Fong-Yuan CHANG, Hui-Yu LEE, Po-Hsiang HUANG
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Publication number: 20190157180Abstract: An integrated circuit (IC) package structure includes an electrical signal path, a low thermal resistance path and a substrate that includes a first device and a second device. The first device and the second device are part of an IC chip. The electrical signal path is from the first device to a top surface of the IC chip. The low thermal resistance path extends from the second device to the top surface of the IC chip. The low thermal resistance path is electrically isolated from the electrical signal path. The second device is thermally coupled to the first device by a low thermal resistance substrate path.Type: ApplicationFiled: November 29, 2018Publication date: May 23, 2019Inventors: Ying-Chih HSU, Alan ROTH, Chuei-Tang WANG, Chih-Yuan CHANG, Eric SOENEN, Chih-Lin CHEN
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Patent number: 10163751Abstract: A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.Type: GrantFiled: July 25, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chih Hsu, Alan Roth, Chuei-Tang Wang, Chih-Yuan Chang, Eric Soenen, Chih-Lin Chen
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Publication number: 20180161929Abstract: A box-type laser processing machine capable of vacuum dedusting includes a chassis; a laser processing area is provided inside the chassis for processing work of a laser output apparatus, and the box-type laser processing machine capable of vacuum dedusting is characterized in that: a plurality of air inlet holes is provided above the laser processing area in the periphery of the chassis, and an air exhaust hole is provided opposite to the laser processing area on the chassis; in this way, when air extraction is performed in the laser processing area inside the chassis by using an air extraction device, air outside the chassis may be guided into the chassis via the plurality of air inlet holes to extract dust generated by processing work out of the chassis via the air exhaust hole.Type: ApplicationFiled: December 14, 2016Publication date: June 14, 2018Inventor: Chih-Lin CHEN
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Publication number: 20180151466Abstract: A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.Type: ApplicationFiled: July 25, 2017Publication date: May 31, 2018Inventors: Ying-Chih HSU, Alan ROTH, Chuei-Tang WANG, Chih-Yuan CHANG, Eric SOENEN, Chih-Lin CHEN
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Publication number: 20180138126Abstract: A package structure includes a first redistribution layer, a molding material, a semiconductor device and an inductor. The molding material is located on the first redistribution layer. The semiconductor device is molded in the molding material. The inductor penetrates through the molding material and electrically connected to the semiconductor device.Type: ApplicationFiled: November 17, 2016Publication date: May 17, 2018Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Lin CHEN, Chung-Hao TSAI, Jeng-Shien HSIEH, Chuei-Tang WANG, Chen-Hua YU, Chih-Yuan CHANG
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Patent number: 8983402Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.Type: GrantFiled: August 13, 2013Date of Patent: March 17, 2015Assignee: National Sun Yat-Sen UniversityInventors: Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Gang-Neng Sung, Tai-Hao Yeh, Chun-Ying Juan, Zong-You Hou
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Publication number: 20150050897Abstract: A transceiver with wake up detection includes a primary control unit, a transmission unit and a receiving unit, the transmission unit comprises a first logic set, a second logic set, a third logic set, a first loop, and a second loop. The first loop outputs a first differential signal, and the second loop outputs a second differential signal. The receiving unit comprises a wake up detection circuit having a first comparator, a second comparator and a fourth logic set. When the first comparator and the second comparator receive a first predetermined level of the first differential signal and a second predetermined level of the second differential signal, the fourth logic set outputs an idle state signal and a data signal to the primary control unit to make an operation mode of the transceiver switched from a low power mode to a normal mode.Type: ApplicationFiled: August 13, 2013Publication date: February 19, 2015Applicant: NATIONAL SUN YAT-SEN UNIVERSITYInventors: Chua-Chin Wang, Chih-Lin Chen, Jie-Jyun Li, Gang-Neng Sung, Tai-Hao Yeh, Chun-Ying Juan, Zong-You Hou
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Publication number: 20130334180Abstract: An automatic compound feeding and recalling laser processing equipment comprising a laser processing machine, a laser mechanism for laser processing and a working platform being disposed in the laser processing machine; a feeding machine and a recalling machine disposing at two opposite ends of the laser processing machine respectively. A feeding shaft is disposed in the feeding machine for unreeling a roll of to-be-processed strip workpiece so that the strip workpiece is passed through the working platform to be processed by laser. A recalling shaft is disposed in the recalling machine for reeling the processed strip workpiece. Thereby, the laser processing can be performed continuously and mass production can be achieved speedily.Type: ApplicationFiled: June 13, 2012Publication date: December 19, 2013Inventors: Che-Min KUNG, Chih-Lin Chen, Ming-Che Su, Jung-Yie Wu
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Publication number: 20130319975Abstract: A laser processing machine with an air curtain structure comprises a machine frame, and a working platform, a processing device, and an air curtain device are disposed on the machine frame. The working platform is used for placing a workpiece. The processing device comprises a rail platform on which a laser output device is disposed. The laser output device is movable on the rail platform and can output laser on the workpiece. The air curtain device comprises at least one air inlet conduit provided with at least one air outlet at a location facing the laser output device on the rail platform. After the air curtain device is connected with an air supply device, the supplied air flows into the air curtain device through the air inlet conduit and is blown toward the laser output device from the air outlet to form an air curtain.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Inventors: CHE-MIN KUNG, HSIEH-CHANG LIN, CHIH-LIN CHEN
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Patent number: 7923770Abstract: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.Type: GrantFiled: June 16, 2008Date of Patent: April 12, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Lin Chen, Kuang-Wen Liu, Hsin-Huei Chen