Patents by Inventor Chih-Lin LEE
Chih-Lin LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12040383Abstract: A method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.Type: GrantFiled: September 2, 2021Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Lin Lee, Choh Fei Yeap, Da-Wen Lin, Chih-Chieh Yeh
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Publication number: 20240044969Abstract: A noise monitoring apparatus includes a row selection circuit, a direct current (DC) cancellation circuit and an amplifier circuit. The row selection circuit selects a row of a DUT array to be a selected row during a readout period, wherein the selected row comprises a plurality of selected DUTs. The DC cancellation circuit is coupled to unselected DUTs of the DUT array during the readout period, generates a DC current signal based on bias current signals from a group of unselected DUTs and subtract the DC current signal from a first noise signal of the selected DUT to generate a second noise signal. The amplifier circuit is coupled to the plurality of selected DUTs of the selected row during the readout period, and amplifies the second noise signal from each of the selected DUTs to generate an output signal.Type: ApplicationFiled: August 2, 2022Publication date: February 8, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Chih-Lin Lee, Kuo-Yu Chou
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Publication number: 20230358864Abstract: An apparatus, a processing circuitry and a method for measuring a distance to an object are provided. The apparatus comprising a light source, a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, a processing circuitry coupled to the DTOF sensor array and comprising a first time to digital converter (TDC) and a second TDC, respectively disposed on opposite sides of the DTOF sensor array, the processing circuitry configured to receive, by the first TDC, a first photon detection signal transmitted by a first pixel, receive, by the second TDC, a second photon detection signal transmitted by the first pixel, and calculate a first distance from the first pixel to the object according to a first arrival time of the first photon detection signal detected by the first TDC and a second arrival time of the second signal detected by the second TDC.Type: ApplicationFiled: May 5, 2022Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Shang-Fu Yeh, Chiao-Yi Huang, Chih-Lin Lee
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Patent number: 11726187Abstract: An apparatus and method for providing a filtering false photon count events for each pixel in a DTOF sensor array are disclosed herein. In some embodiments, the apparatus includes: a light source configured to emit a modulated signal towards the object; a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, wherein the DTOF sensor array comprises a plurality of single-photon avalanche diodes (SPADs); and processing circuitry configured to receive photon event detection signals from a center pixel and a plurality of pixels orthogonally and diagonally adjacent to the center pixel and output a valid photon detection signal, in response to determining whether a sum of the received photon event detection signals is greater than a predetermined threshold.Type: GrantFiled: October 30, 2020Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Meng-Hsiu Wu, Chih-Lin Lee, Calvin Yi-Ping Chao, Shang-Fu Yeh
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Publication number: 20230243939Abstract: A method of a sensing device, comprising steps of emitting, by a light source of the sensing device, a light pulse in each of n cycles; measuring, by a single photon avalanche diodes array of the sensing device, a time-of-flight value with a resolution of m in each of the n cycles to generate n raw data frames based on a reflected light of the light pulse; performing, by a pre-processing circuit of the sensing device, a pre-processing operation to n raw data frames to generate k pre-processed data frames, wherein m, n and k are natural numbers, and k is smaller than n; and generating, by post-processor of the sensing device, a histogram according to the k pre-processed data frames and analyzing the histogram to output a depth result.Type: ApplicationFiled: April 11, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
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Patent number: 11644547Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal.Type: GrantFiled: June 27, 2019Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
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Patent number: 11605627Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: GrantFiled: June 3, 2021Date of Patent: March 14, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 11579263Abstract: Disclosed is a time-of-flight sensing apparatus and method.Type: GrantFiled: October 17, 2019Date of Patent: February 14, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Meng-Hsiu Wu, Chih-Lin Lee, Calvin Yi-Ping Chao, Shang-Fu Yeh
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Patent number: 11569346Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.Type: GrantFiled: July 16, 2021Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
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Publication number: 20220137192Abstract: An apparatus and method for providing a filtering false photon count events for each pixel in a DTOF sensor array are disclosed herein. In some embodiments, the apparatus includes: a light source configured to emit a modulated signal towards the object; a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, wherein the DTOF sensor array comprises a plurality of single-photon avalanche diodes (SPADs); and processing circuitry configured to receive photon event detection signals from a center pixel and a plurality of pixels orthogonally and diagonally adjacent to the center pixel and output a valid photon detection signal, in response to determining whether a sum of the received photon event detection signals is greater than a predetermined threshold.Type: ApplicationFiled: October 30, 2020Publication date: May 5, 2022Inventors: Chin YIN, Meng-Hsiu WU, Chih-Lin LEE, Calvin Yi-Ping CHAO, Shang-Fu YEH
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Patent number: 11289529Abstract: A pixel circuit includes: a photodiode capable of generating electrical current according to an incoming light signal; a control circuit coupled to the photodiode for selectively coupling a cathode of the photodiode to a first reference voltage to generate the electrical current according to a first control signal; and an output circuit coupled to the control circuit for selectively coupling a second reference voltage to a connecting terminal between the control circuit and the output circuit and to generate an output signal according to a reset signal and a select signal.Type: GrantFiled: April 1, 2020Date of Patent: March 29, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Meng-Hsiu Wu
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Patent number: 11199444Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.Type: GrantFiled: June 27, 2019Date of Patent: December 14, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao
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Publication number: 20210343838Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO
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Publication number: 20210313379Abstract: A pixel circuit includes: a photodiode capable of generating electrical current according to an incoming light signal; a control circuit coupled to the photodiode for selectively coupling a cathode of the photodiode to a first reference voltage to generate the electrical current according to a first control signal; and an output circuit coupled to the control circuit for selectively coupling a second reference voltage to a connecting terminal between the control circuit and the output circuit and to generate an output signal according to a reset signal and a select signal.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: CHIN YIN, CHIH-LIN LEE, SHANG-FU YEH, MENG-HSIU WU
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Publication number: 20210288045Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 11075267Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: GrantFiled: December 16, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
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Patent number: 11037922Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: GrantFiled: April 15, 2020Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 11006064Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.Type: GrantFiled: September 16, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Po-Sheng Chou, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20210084247Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Po-Sheng Chou, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20200408885Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu