Patents by Inventor Chih-Lin LEE

Chih-Lin LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240188251
    Abstract: A monitoring and alerting method for a liquid-cooling system includes monitoring a thermal resistance variation of a cold plate of the liquid-cooling system and sending an alert related to the thermal resistance variation. Furthermore, a liquid-cooling system and an electronic device including the same are provided. The liquid-cooling system includes a liquid-cooling module including a cold plate; and a monitoring and alerting module including a control unit, an inlet thermometer in communication with the control unit for measuring a temperature of a liquid inlet of the cold plate, and a heat source thermometer in communication with the control unit for measuring a temperature of a heat source in thermal contact with the cold plate. The control unit produces an alert according to a thermal resistance variation calculated by the inlet thermometer, the heat source thermometer, and a power of the heat source.
    Type: Application
    Filed: May 2, 2023
    Publication date: June 6, 2024
    Inventors: CHIH CHENG LEE, Tzu-Wei Gu, Chun-Chieh Huang, Yu-Lin Chen
  • Publication number: 20240154015
    Abstract: A method includes forming a first fin and a second fin protruding from a frontside of a substrate, forming a gate stack over the first and second fins, forming a dielectric feature dividing the gate stack into a first segment engaging the first fin and a second segment engaging the second fin, and growing a first epitaxial feature on the first fin and a second epitaxial feature on the second fin. The dielectric feature is disposed between the first and second epitaxial features. The method also includes performing an etching process on a backside of the substrate to form a backside trench, and forming a backside via in the backside trench. The backside trench exposes the dielectric feature and the first and second epitaxial features. The backside via straddles the dielectric feature and is in electrical connection with the first and second epitaxial features.
    Type: Application
    Filed: March 22, 2023
    Publication date: May 9, 2024
    Inventors: Jui-Lin CHEN, Hsin-Wen SU, Chih-Ching WANG, Chen-Ming LEE, Chung-I YANG, Yi-Feng TING, Jon-Hsu HO, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 11972975
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a masking structure with first openings over a semiconductor substrate and correspondingly forming metal layers in the first openings. The method also includes recessing the masking structure to form second openings between the metal layers and forming a sacrificial layer surrounded by a first liner in each of the second openings. In addition, after forming a second liner over the sacrificial layer in each of the second openings, the method includes removing the sacrificial layer in each of the second openings to form a plurality of air gaps therefrom.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai, Hsin-Chieh Yao, Chih-Wei Lu, Chung-Ju Lee, Shau-Lin Shue
  • Publication number: 20240097034
    Abstract: A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Tsung-Lin Lee, Chih-Hao Chang, Chih-Hsin Ko, Feng Yuan, Jeff J. Xu
  • Publication number: 20240088091
    Abstract: A method for manufacturing a package structure includes: providing a first electrical element and a second electrical element on a surface of a first carrier, wherein the second electrical element is shifted with respect to the first electrical element; and moving the first electrical element along at least one direction substantially parallel with the surface of the first carrier until a first surface of the first electrical element is substantially aligned with a first surface of the second electrical element from a top view.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Lin SHIH, Chih-Cheng LEE
  • Publication number: 20240088001
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
  • Patent number: 11929258
    Abstract: An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Ming Chang, Chih-Ming Lai, Ru-Gun Liu, Tsai-Sheng Gau, Chung-Ju Lee, Tien-I Bao, Shau-Lin Shue
  • Publication number: 20240073559
    Abstract: Electrical Phase Detection Auto Focus. In one embodiment, an image sensor includes a plurality of pixels arranged in rows and columns of a pixel array disposed in a semiconductor material. Each pixel includes a plurality of photodiodes configured to receive incoming light through an illuminated surface of the semiconductor material. The plurality of pixels includes at least one autofocusing phase detection (PDAF) pixel having: a first subpixel without a light shielding, and a second subpixel without the light shielding. Autofocusing of the image sensor is at least in part determined based on different electrical outputs of the first subpixel and the second sub pixels.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Young Woo Jung, Chih-Wei Hsiung, Vincent Venezia, Zhiqiang Lin, Sang Joo Lee
  • Publication number: 20240044969
    Abstract: A noise monitoring apparatus includes a row selection circuit, a direct current (DC) cancellation circuit and an amplifier circuit. The row selection circuit selects a row of a DUT array to be a selected row during a readout period, wherein the selected row comprises a plurality of selected DUTs. The DC cancellation circuit is coupled to unselected DUTs of the DUT array during the readout period, generates a DC current signal based on bias current signals from a group of unselected DUTs and subtract the DC current signal from a first noise signal of the selected DUT to generate a second noise signal. The amplifier circuit is coupled to the plurality of selected DUTs of the selected row during the readout period, and amplifies the second noise signal from each of the selected DUTs to generate an output signal.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Chih-Lin Lee, Kuo-Yu Chou
  • Publication number: 20230358864
    Abstract: An apparatus, a processing circuitry and a method for measuring a distance to an object are provided. The apparatus comprising a light source, a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, a processing circuitry coupled to the DTOF sensor array and comprising a first time to digital converter (TDC) and a second TDC, respectively disposed on opposite sides of the DTOF sensor array, the processing circuitry configured to receive, by the first TDC, a first photon detection signal transmitted by a first pixel, receive, by the second TDC, a second photon detection signal transmitted by the first pixel, and calculate a first distance from the first pixel to the object according to a first arrival time of the first photon detection signal detected by the first TDC and a second arrival time of the second signal detected by the second TDC.
    Type: Application
    Filed: May 5, 2022
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Shang-Fu Yeh, Chiao-Yi Huang, Chih-Lin Lee
  • Patent number: 11726187
    Abstract: An apparatus and method for providing a filtering false photon count events for each pixel in a DTOF sensor array are disclosed herein. In some embodiments, the apparatus includes: a light source configured to emit a modulated signal towards the object; a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, wherein the DTOF sensor array comprises a plurality of single-photon avalanche diodes (SPADs); and processing circuitry configured to receive photon event detection signals from a center pixel and a plurality of pixels orthogonally and diagonally adjacent to the center pixel and output a valid photon detection signal, in response to determining whether a sum of the received photon event detection signals is greater than a predetermined threshold.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Yin, Meng-Hsiu Wu, Chih-Lin Lee, Calvin Yi-Ping Chao, Shang-Fu Yeh
  • Publication number: 20230243939
    Abstract: A method of a sensing device, comprising steps of emitting, by a light source of the sensing device, a light pulse in each of n cycles; measuring, by a single photon avalanche diodes array of the sensing device, a time-of-flight value with a resolution of m in each of the n cycles to generate n raw data frames based on a reflected light of the light pulse; performing, by a pre-processing circuit of the sensing device, a pre-processing operation to n raw data frames to generate k pre-processed data frames, wherein m, n and k are natural numbers, and k is smaller than n; and generating, by post-processor of the sensing device, a histogram according to the k pre-processed data frames and analyzing the histogram to output a depth result.
    Type: Application
    Filed: April 11, 2023
    Publication date: August 3, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
  • Patent number: 11644547
    Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 9, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
  • Patent number: 11605627
    Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: March 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
  • Patent number: 11579263
    Abstract: Disclosed is a time-of-flight sensing apparatus and method.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin Yin, Meng-Hsiu Wu, Chih-Lin Lee, Calvin Yi-Ping Chao, Shang-Fu Yeh
  • Patent number: 11569346
    Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: January 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
  • Publication number: 20220137192
    Abstract: An apparatus and method for providing a filtering false photon count events for each pixel in a DTOF sensor array are disclosed herein. In some embodiments, the apparatus includes: a light source configured to emit a modulated signal towards the object; a direct time of flight (DTOF) sensor array configured to receive a reflected signal from the object, wherein the DTOF sensor array comprises a plurality of single-photon avalanche diodes (SPADs); and processing circuitry configured to receive photon event detection signals from a center pixel and a plurality of pixels orthogonally and diagonally adjacent to the center pixel and output a valid photon detection signal, in response to determining whether a sum of the received photon event detection signals is greater than a predetermined threshold.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Chin YIN, Meng-Hsiu WU, Chih-Lin LEE, Calvin Yi-Ping CHAO, Shang-Fu YEH
  • Patent number: 11289529
    Abstract: A pixel circuit includes: a photodiode capable of generating electrical current according to an incoming light signal; a control circuit coupled to the photodiode for selectively coupling a cathode of the photodiode to a first reference voltage to generate the electrical current according to a first control signal; and an output circuit coupled to the control circuit for selectively coupling a second reference voltage to a connecting terminal between the control circuit and the output circuit and to generate an output signal according to a reset signal and a select signal.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: March 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Meng-Hsiu Wu
  • Patent number: 11199444
    Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao
  • Publication number: 20210343838
    Abstract: A semiconductor device includes a source/drain diffusion area, a first doped region and a gate. The source/drain diffusion area, defined between a first isolation structure and a second isolation structure, includes a source region, a drain region and a device channel. The first doped region, disposed along a first junction between the device channel and the first isolation structure, is separated from at least one of the source region and the drain region. The first doped region has a dopant concentration higher than that of the device channel. The gate is disposed over the source/drain diffusion area. The first doped region is located within a projected area of the gate onto the source/drain diffusion area, the first isolation structure and the second isolation structure. A length of the first doped region is shorter than a length of the gate in a direction from the source region to the drain region.
    Type: Application
    Filed: July 16, 2021
    Publication date: November 4, 2021
    Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO