Patents by Inventor Chih-Lin LEE
Chih-Lin LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210288045Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: ApplicationFiled: June 3, 2021Publication date: September 16, 2021Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 11075267Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: GrantFiled: December 16, 2019Date of Patent: July 27, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
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Patent number: 11037922Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: GrantFiled: April 15, 2020Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 11006064Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.Type: GrantFiled: September 16, 2019Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin Yin, Po-Sheng Chou, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20210084247Abstract: A CMOS image sensor, and a method of operating a pixel array by a CMOS image sensor is provided. The CMOS image sensor includes a sensor, and a readout circuit. The sensor is configured to generate a first voltage signal and a first reset signal. The readout circuit is configured to perform a first readout operation by reading out the first reset signal and the first voltage signal simultaneously at a first predetermined time. After the first readout operation, the readout circuit turns on a plurality of switches to obtain a common-mode signal by making the first reset signal equal to the first voltage signal and re-perform a second readout operation by reading out the common-mode signal at a second predetermined time. The first predetermined time and the second predetermined time do not overlap each other.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Po-Sheng Chou, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20200408885Abstract: A sensing device that is configured to determine a depth result based on time-of-flight value is introduced. The sensing device includes a delay locked loop circuit, a plurality of time-to-digital converters, a multiplexer and a digital integrator. The delay locked loop circuit is configured to output a plurality of delay clock signals through output terminals of the delay locked loop circuit. The plurality of time-to-digital converters include a plurality of latches. The multiplexer is configured to select a sub-group of m latches among the latches of the plurality of time-to-digital converters to be connected to the output terminals of the delay locked loop circuit according to a control signal.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin Yin, Shang-Fu Yeh, Calvin Yi-Ping Chao, Chih-Lin Lee, Meng-Hsiu Wu
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Publication number: 20200243510Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: ApplicationFiled: April 15, 2020Publication date: July 30, 2020Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20200174105Abstract: Disclosed is a time-of-flight sensing apparatus and method.Type: ApplicationFiled: October 17, 2019Publication date: June 4, 2020Inventors: Chin YIN, Meng-Hsiu WU, Chih-Lin LEE, Calvin Yi-Ping CHAO, Shang-Fu YEH
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Patent number: 10636782Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: GrantFiled: November 16, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 10638078Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.Type: GrantFiled: June 1, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao, Chih-Lin Lee, Chin Yin
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Publication number: 20200119144Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO
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Publication number: 20200018642Abstract: A self-calibration time-to-digital converter (TDC) integrated circuit for single-photon avalanche diode (SPAD) based depth sensing is disclosed. The circuit includes a SPAD matrix with a plurality of SPAD pixels arranged in m rows and n columns, the SPAD pixels in each column of SPAD pixels are connected by a column bus; a global DLL unit with n buffers and n clock signals; and an image signal processing unit for receiving image signals from the column TDC array. The circuit can also include a row control unit configured to enable one SPAD pixel in each row for a transmitting signal; a circular n-way multiplexer for circularly multiplexing n clock signals in the global DLL unit; a column TDC array with n TDCs, each TDC further comprises a counter and a latch, the latch of each TDC is connected to the circular n-way multiplexer for circular multiplexing.Type: ApplicationFiled: June 27, 2019Publication date: January 16, 2020Inventors: Chin Yin, Chih-Lin Lee, Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao
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Patent number: 10510835Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: GrantFiled: April 27, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Kuo-Yu Chou, Seiji Takahashi, Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Calvin Yi-Ping Chao
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Publication number: 20190373200Abstract: A counter, a counting method and an apparatus for image sensing are introduced in the present disclosure. The counter includes a plurality of dual phase clock generators and a plurality of column counters. Each of the plurality of dual phase clock generator receives a common clock signal and generates dual phase clock signals which comprise a first clock signal and a second clock signal according to the common clock signal. Each of the plurality of column counters is coupled to one of the plurality of dual phase clock generators to receive the first clock signal and the second clock signal, and is configured to output a counting value according to the first clock signal and the second clock signal. Each of the plurality of dual phase clock generators provides the first clock signal and the second clock signal to a group of the plurality of column counters.Type: ApplicationFiled: June 1, 2018Publication date: December 5, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Fu Yeh, Kuo-Yu Chou, Calvin Yi-Ping Chao, Chih-Lin Lee, Chin Yin
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Publication number: 20190333989Abstract: A semiconductor device comprises a source/drain diffusion area, and a first doped region. The source/drain diffusion area is defined between a first isolation structure and a second isolation structure. The source/drain diffusion area includes a source region, a drain region, and a device channel. The device channel is between the source region and the drain region. The first doped region is disposed along a first junction between the device channel and the first isolation structure in a direction from the source region to the drain region. The first doped region is separated from at least one of the source region and the drain region, and has a dopant concentration higher than that of the device channel. The semiconductor device of the present disclosure has low random telegraph signal noise and fewer defects.Type: ApplicationFiled: April 27, 2018Publication date: October 31, 2019Inventors: KUO-YU CHOU, SEIJI TAKAHASHI, SHANG-FU YEH, CHIH-LIN LEE, CHIN YIN, CALVIN YI-PING CHAO
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Patent number: 10277849Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: GrantFiled: March 30, 2018Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang
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Patent number: 10270992Abstract: A device includes a current source and sampling units. Each of the sampling units includes a transistor and a capacitor electrically coupled to a gate of the transistor. The sampling units are sequentially activated such that the capacitor samples a voltage of a column line of a pixel array and are activated together such that the transistor is turned on according to the sampled voltage of the capacitor, to drain a current from the current source through an output node to generate an output voltage thereat.Type: GrantFiled: November 30, 2017Date of Patent: April 23, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shang-Fu Yeh, Chih-Lin Lee, Chin Yin, Kuo-Yu Chou
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Publication number: 20190088640Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: ApplicationFiled: November 16, 2018Publication date: March 21, 2019Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Patent number: 10157906Abstract: Circuits and methods for protecting a device are provided. A first device to be protected includes a gate dielectric of a first thickness. A second device includes a gate dielectric of a second thickness that is less than the first thickness. A gate is shared by the first device and the second device.Type: GrantFiled: August 3, 2016Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Shang-Fu Yeh, Yi-Ping Chao, Chih-Lin Lee
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Publication number: 20180227531Abstract: A system and method of routing multiple pixels from a single column in a CMOS (complementary metal-oxide semiconductor) image sensors (CIS) to a plurality of column analog-to-digital converters (ADCs) is disclosed. The CIS includes an array of pixel elements having a plurality of rows and a plurality of columns. A plurality of column-out signal paths is coupled to each of the plurality of columns of the array of pixel elements. A column routing matrix is coupled to each plurality of column-out signal paths for each of the plurality of columns. A plurality of analog-to-digital converters (ADCs) are coupled to the column routing matrix. The column routing matrix is configured to route at least one column-out signal path to each of the plurality of ADCs during a down-sampling read operation.Type: ApplicationFiled: March 30, 2018Publication date: August 9, 2018Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Chin-Hao Chang, Kuo-Yu Chou, Shang-Fu Yeh, Chih-Lin Lee, Chiao-Yi Huang