Abstract: Disclosed in embodiments of the present invention are a method for processing scrambling information, a terminal, and a network apparatus. The method comprises: a network apparatus determining first information, wherein the first information is associated with at least one piece of the following information: a transmission point, a multiple-input multiple-output (MIMO) data layer of the transmission point, a code block transmitted from the transmission point, and a data channel and a preamble transmitted from the transmission point; and the network apparatus determining, at least on the basis of the first information, initialization information for scrambling.

Abstract: The present disclosure relates an integrated chip. The integrated chip includes a semiconductor device arranged along a first side of a semiconductor substrate. The semiconductor substrate has one or more sidewalls extending from the first side of the semiconductor substrate to an opposing second side of the semiconductor substrate. A dielectric liner lines the one or more sidewalls of the semiconductor substrate. A through-substrate-via (TSV) is arranged between the one or more sidewalls and is separated from the semiconductor substrate by the dielectric liner. The TSV has a first width at a first distance from the second side and a second width at a second distance from the second side. The first width is smaller than the second width and the first distance is smaller than the second distance.

Abstract: In some embodiments, the present disclosure relates to a process tool that includes a lithography apparatus arranged over a wafer chuck and an immersion hood apparatus laterally around the lithography apparatus. The lithography apparatus includes a photomask arranged between a light source and a lens. The immersion hood apparatus comprises input piping, output piping, and extractor piping. The input piping is arranged on a lower surface of the immersion hood apparatus and configured to distribute a liquid between the lens and the wafer chuck. The output piping is arranged on the lower surface of the immersion hood apparatus and configured to contain the liquid arranged between the lens and the wafer chuck. The extractor piping is arranged on an outer sidewall of the immersion hood apparatus and configured to remove any liquid above the wafer chuck that is outside of the immersion hood apparatus.

Abstract: An electronic device having an aluminum or copper foil heat dissipator includes a casing, an electronic structure disposed in the casing, and an aluminum or copper foil heat dissipator. A surface of the electronic structure has a heat source element. The aluminum or copper foil heat dissipator is a 3D aluminum or copper foil structure formed by stamping and includes a bottom, a surrounding portion, and a 3D space formed between the bottom and the surrounding portion. The bottom is thermal conductively coupled to the heat source element. A surface of the aluminum or copper foil heat dissipator is partially/entirely thermal conductively coupled to an inner surface of the casing. With the characteristics of aluminum or copper foil that is easy to expand into a 3D shape during processing and could closely fit the inner surface, the heat generated by the heat source element could be dissipated from the 3D aluminum or copper foil with a large contact area, achieving better heat dissipation effect.

Abstract: Provided include a beam modulation apparatus for modulating an input light field and a projection system containing the apparatus. The input light field has a first light field and a second light field, having a difference of 90° in their polarization states. The apparatus includes a PBS prism, a first LCOS panel and a second LCOS panel. The first and the second LCOS panel are respectively over a side surface of the PBS prism opposing to an optical incident surface and an optical exit surface. Each LCOS panel comprises a plurality of pixels over a reflective surface thereof, with each pixel controllably switched on or off such that a polarity state of a light beam reflected by a portion of the reflective surface corresponding thereto is changed or remains unchanged. This beam modulation apparatus can be applied in a projection system, such as a laser TV projection system.

Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure over a substrate and forming a sealing layer surrounding the dummy gate structure. The method includes forming a spacer covering the sealing layer and removing the dummy gate structure to form a trench. The method further includes forming an interfacial layer and a gate dielectric layer. The method further includes forming a capping layer over the gate dielectric layer and partially oxidizing the capping layer to form a capping oxide layer. The method further includes forming a work function metal layer over the capping oxide layer and forming a gate electrode layer over the work function metal layer. In addition, a bottom surface of the capping oxide layer is higher than a bottom surface of the spacer.

Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a first inter-metal dielectric (IMD) structure disposed over a semiconductor substrate. A metal-insulator-metal (MIM) device is disposed over the first IMD structure. The MIM device comprises at least three metal plates that are spaced from one another. The MIM device further comprises a plurality of capacitor insulator structures, where each of the plurality of capacitor insulator structures are disposed between and electrically isolate neighboring metal plates of the at least three metal plates.

Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.

Abstract: An electronic device and an antenna module are provided. The electronic device includes a metal housing and the antenna module disposed. The metal housing has a slot, and the slot has an open end. The antenna module includes a carrier, a feeding element, a radiating element connected to the feeding element, and a grounding element. The radiating element is disposed on a first surface of the carrier. An orthogonal projection of the radiating element that is projected onto the metal housing at least partially overlaps with the slot. The grounding element includes a first grounding portion and a second grounding portion electrically connected to each other. The radiating element and the first grounding portion are spaced apart from each other by a first coupling gap, and the radiating element and the second grounding portion are spaced apart from each other by a second coupling gap.

Abstract: An antenna module and an electronic device are provided. The antenna module is disposed in a housing of the electronic device. The antenna module includes a first radiating element, a second radiating element, and a feeding element. The first radiating element includes a first radiating portion, a second radiating portion, and a feeding portion. The feeding portion is connected between the first radiating portion and the second radiating portion. A length of the first radiating portion is greater than a length of the second radiating portion. The second radiating element includes a connecting portion, a third radiating portion, and a fourth radiating portion. The connecting portion is connected between the third radiating portion and the fourth radiating portion. A length of the third radiating portion and a length of the fourth radiating portion are not equal to each other.

Abstract: A method of controlling a wafer stage includes moving the wafer stage to position an immersion hood over a first sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a second sensor in the wafer stage. The method further includes moving the wafer stage to position the immersion hood over a first particle capture area on the wafer stage after moving the wafer stage to position the immersion hood over the second sensor. The method further includes moving the wafer stage to define a routing track over the first particle capture area. The method further includes moving the wafer stage to position the immersion hood over an area for receiving a wafer on the wafer stage after defining the routing track over the first particle capture area.

Abstract: A semiconductor structure includes substrate, semiconductor layers, source/drain features, metal oxide layers, and a gate structure. The semiconductor layers extend in an X-direction and over the substrate. The semiconductor layers are spaced apart from each other in a Z-direction. The source/drain features are on opposite sides of the semiconductor layers in the X-direction. The metal oxide layers cover bottom surfaces of the semiconductor layers. The gate structure wraps around the semiconductor layers and the metal oxide layers. The metal oxide layers are in contact with the gate structure.

Abstract: A semiconductor device includes a fin-shape base protruding from a substrate, channel structures suspended above the fin-shape base, a gate structure wrapping around each of the channel structures, a source/drain (S/D) epitaxial feature abutting the channel structures and directly above a top surface of the fin-shape base, inner spacers interposing the S/D epitaxial feature and the gate structure, and a dielectric layer disposed vertically between the top surface of the fin-shape base and a bottom surface of the S/D epitaxial feature.

Abstract: A method of forming a memory device including forming a bottom electrode via (BEVA) in a dielectric layer, forming a magnetic tunnel junction (MTJ) multilayer structure over the BEVA, forming a top electrode on the MTJ multilayer structure, patterning the MTJ multilayer structure using the top electrode as an etch mask to form a MTJ stack, forming a first interlayer dielectric (ILD) layer over the MTJ stack, and after forming the first ILD layer, forming a ferromagnetic metal that exerts a magnetic field on the MTJ stack.

Abstract: A phase-locked loop (PLL) circuit includes a PLL core circuit, at least one lookup table, and a control circuit. The PLL core circuit generates an output clock under an open-loop calibration phase and a closed-loop calibration phase. The control circuit loads PLL parameters that are derived from the at least one lookup table to the PLL core circuit, performs open-loop calibration upon a first part of the PLL parameters under the open-loop calibration phase of the PLL core circuit, and performs closed-loop calibration upon a second part of the PLL parameters under the closed-loop calibration phase of the PLL core circuit.

Abstract: The present disclosure is directed to motor system for a multi-RET actuator system. The motor system includes a rotor configured to rotate within an interior cavity of a stator, a drive shaft coupled to the rotor and to a drive assembly of the multi-RET actuator system, an annular disc surrounding the stator, the annular disc is coupled to the rotor such that rotation of the rotor causes simultaneous rotation of the annular disc, a plurality of spaced apart magnets embedded within the annular disc, a HALL effect sensor, and a motor speed controller in communication with the rotor and the HALL effect sensor. Methods for controlling the position and speed of a motor system are also described herein.

Abstract: The present disclosure provides an immersion cooling system for a server cabinet including a plurality of server boxes, a cooling tank and a plurality of liquid connecting pipes. Each server box includes an electronic device immersed in the cooling liquid, and the electronic device generates a thermal energy so that part of the cooling liquid evaporates into a hot vapor. The cooling tank is connected to the plurality of server boxes and includes a condenser and a storage part. The condenser is connected to each server box and condenses the hot vapor to form the cooling liquid. The storage part storages the cooling liquid from the condenser. Two ends of the liquid connecting pipe is connected to the storage part and the server box respectively. The cooling liquid in the storage part and the cooling liquid of each server box are maintained in a same liquid level.

Abstract: A charge pump of a phase-locked loop (PLL) circuit includes a current source circuit, a current sink circuit, and a biasing circuit. The biasing circuit includes a current digital-to-analog converter (IDAC) and a low-pass filter (LPF). The IDAC provides a reference current in response to a current value setting, wherein a first voltage is established due to the reference current. The LPF applies low-pass filtering to the first voltage to generate a filter output as a second voltage, wherein bias voltages of the current source circuit and the current sink circuit are controlled by the second voltage.