Abstract: Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.

Abstract: A respiratory assistance system including a humidification apparatus used for delivery of heated and humidified gases to a patient includes a humidification chamber with an associated heater and sensor, an inspiratory conduit with an associated heater and sensor, and an unheated patient interface, such as a face mask. A controller of the humidification apparatus is configured to determine a gas source and change the set point accordingly to maintain patient comfort regardless of the humidity level of the gas source.

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: A dynamic protection circuit including an adjustment circuit, a detection circuit, a control circuit, and a counter circuit is provided. The adjustment circuit adjusts an output voltage based on a predetermined value. The detection circuit detects whether the output voltage is higher than an upper-limit value or lower than a lower-limit value. The control circuit changes the predetermined value and disables the detection circuit while the predetermined value is being changed. The counter circuit starts to adjust a count value in response to the detection circuit being disabled. In response to the counter circuit adjusting the count value, the control circuit adjusts the upper-limit value and the lower-limit value to be proportional to the output voltage. In response to the count value being equal to a target value, the counter circuit enables the detection circuit.

Abstract: An example electronic device includes a network communication interface to connect to a conference server, a central control device communication interface to connect to a local central control device, a microphone and a processor. The processor is to receive audio at the microphone and send the audio to the local central control device and to the conference server. The processor is to send the audio to the local central control device such that it is received by a nearby electronic device before the audio is received from the conference server by the nearby electronic device.

Abstract: A pixel structure includes a first light-emitting diode for emitting a first light, wherein the first light-emitting diode has a first semiconductor layer, a first light-emitting surface, and a first electrode under the first semiconductor layer away from the first light-emitting surface; a second light-emitting diode for emitting a second light, wherein the second light-emitting diode has a second semiconductor layer, a second light-emitting surface, and a second electrode under the second semiconductor layer away from the second light-emitting surface; a dielectric layer surrounding and contacting the first semiconductor layer and the second light-emitting diode and exposing the first light-emitting surface, the first electrode, the second light-emitting surface and the second electrode; a common conductive structure having a semiconductor layer and a metal layer; and a light-transmitting conductive layer covering and electrical connecting the first light-emitting diode, the second light-emitting diode and

Abstract: An electronic device includes a light scattering switching element, a light absorbing switching element and a thermal insulation layer. The light absorbing switching element is disposed opposite to the light scattering switching element. The thermal insulation layer is disposed between the light scattering switching element and the light absorbing switching element, wherein the thermal conductivity of the thermal insulation layer is less than 50×10?3 W·m?1·K?1.

Abstract: A control chip providing power to a sink device and including a connection port, an encoder, a decoder, and a control circuit is provided. The connection port provides an output voltage and an inquiry signal to the sink device, and receives an acknowledgement signal provided by the sink device. The encoder generates the inquiry signal. The decoder decodes the acknowledgement signal to generate a decoded result. In a compensation mode, the control circuit obtains an actual voltage received by the sink device according to the decoded result and adjusts the output voltage according to the actual voltage received by the sink device. In a setting mode, the control circuit obtains a protect-point voltage of the sink device according to the decoded result and adjusts the output voltage according to the protect-point voltage of the sink device to prevent the output voltage from being higher than the protect-point voltage.

Abstract: A detachable device includes a base, an object, and a latching structure. The object is detachably disposed over the base and has a fastening part. The latching structure is for detachably connecting the base and the object and includes a main body disposed on the base with a distance from the base. The main body includes a buckle part and a release part. The buckle part is for detachably buckling with the fastening part of the object. The release part is connected to the buckle part and is arranged on a side of the buckle part away from the fastening part. When being pushed by an external force, the release part drives the buckle part away from the fastening part, and the object is detached from the base.

Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: A semiconductor package structure having a frontside redistribution layer, a stacking structure disposed over the frontside redistribution layer and having a first semiconductor die and a second semiconductor die over the first semiconductor die. A backside redistribution layer is disposed over the stacking structure, a first intellectual property (IP) core is disposed in the stacking structure and electrically coupled to the frontside redistribution layer through a first routing channel. A second IP core is disposed in the stacking structure and is electrically coupled to the backside redistribution layer through a second routing channel, wherein the second routing channel is different from the first routing channel and electrically insulated from the frontside redistribution layer.

Abstract: An illuminating device including a light-emitting element array and a plurality of light-diffusing elements is provided. The light-emitting element array includes a plurality of discrete light-emitting areas. The plurality of light-diffusing elements respectively correspond to the light-emitting areas, and each light-diffusing element includes a light-entering surface and a light-exiting surface. The light beams emitted by the light-emitting areas respectively enter the corresponding light-diffusing element via the corresponding light-entering surface. After the light beams respectively leave the corresponding light-diffusing element via the corresponding light-exiting surface, the light beams respectively form a plurality of illumination beams. The illumination beams appear in an array form for illumination.

Abstract: A semiconductor structure and forming method thereof are provided. A substrate includes a first region, a second region, and a boundary region defined between the first region and the second region. An isolation structure is disposed in the boundary region. An upper surface of the isolation structure has a stepped profile. A first boundary dielectric layer and a second boundary dielectric layer are disposed over the isolation structure. The first boundary dielectric layer is substantially conformal with respect to the stepped profile of the isolation structure.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate comprising a semiconductor substrate and an insulator layer over the semiconductor substrate; bonding a silicon layer to the composite substrate; depositing a capping layer over the silicon layer; forming a trench through the capping layer, the silicon layer and the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench; removing the capping layer to form an epitaxial layer from the silicon layer and the initial epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: Disclosed is a die-bonding method which provides a target substrate having a circuit structure with multiple electrical contacts and multiple semiconductor elements each semiconductor element having a pair of electrodes, arranges the multiple semiconductor elements on the target substrate with the pair of electrodes of each semiconductor element aligned with two corresponding electrical contacts of the target substrate, and applies at least one energy beam to join and electrically connect the at least one pair of electrodes of every at least one of the multiple semiconductor elements and the corresponding electrical contacts aligned therewith in a heating cycle by heat carried by the at least one energy beam in the heating cycle. The die-bonding method delivers scattering heated dots over the target substrate to avoid warpage of PCB and ensures high bonding strength between the semiconductor elements and the circuit structure of the target substrate.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.

Abstract: The present disclosure describes a semiconductor structure that includes a channel region, a source region adjacent to the channel region, a drain region, a drift region adjacent to the drain region, and a dual gate structure. The dual gate structure includes a first gate structure over portions of the channel region and portions of the drift region. The dual gate structure also includes a second gate structure over the drift region.

Abstract: The application discloses a semiconductor device and a semiconductor device manufacturing method. The semiconductor device includes: a substrate; a circuit macro on the substrate; a plurality of metal layers over the substrate, wherein the plurality of metal layers include a first power mesh; and a plurality of power switch circuits on the substrate, wherein the power switch circuits selectively couple a power to the first power mesh according to a control signal, and the power switch circuits are arranged in sequence, wherein a control signal output terminal of each first power switch circuit is coupled to a control signal input terminal of a following first power switch circuit, so that the control signal passes through the first power switch circuits sequentially.