Abstract: A radio frequency (RF) tamper detector of an electronic device can offer improved chassis intrusion monitoring to protect the device from software and hardware-based tampering. The tamper detector can monitor RF noise levels in a first frequency band and in a second frequency band to calculate an RF noise level moving average for each frequency band. If the moving averages in both frequency bands exceed a RF noise threshold, the tamper detector can set a cover removal flag to indicate that a cover of the device housing has been removed. The tamper detector can cause the electronic device to lock or disable a system BIOS when cover removal is detected. Additionally, the electronic device can notify remote monitoring systems (e.g., operated by an IT administrator or warranty support center) to receive additional instructions to secure the device.

Abstract: An antenna structure is provided. The antenna structure includes a conductor substrate, a coupling feed-in element and a shielding element. The conductor substrate has a slot. The coupling feed-in element, partly overlapping the slot, is disposed on the conductor substrate. The shielding element, partly overlapping the slot, is separated from the coupling feed-in element and disposed on the conductor substrate, wherein the shielding element is movable along the slot.

Abstract: An electronic device is disclosed. The electronic device includes a first electronic component and a first interposer. The first electronic component is disposed under the interposer and includes a logic circuit and a power delivery circuit disposed between the interposer and the logic circuit. The interposer and the power delivery circuit are collectively configured to function as a power delivery structure which is electrically connected to the logic circuit.

Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.

Abstract: An additive compound for dyeing an aluminum or aluminum alloy substrate after anodic oxidation to provide better uniformity in dyeing and hence a better finished appearance includes a main agent, an auxiliary agent, a pH stabilizer, an antibacterial agent, and a moderating agent. The antibacterial agent includes at least one of sorbic acid, fluconazole, itraconazole, artemisia argyi, benzyl alcohol, benzoic acid, salicylic acid, and boric acid. The moderating agent includes at least one of amino acid, amino salt, sulfate, nitrate, and chloride. An additive solution and a dyeing method are also provided, the use of the compound also allows for a more rapid dyeing process.

Abstract: In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a shield structure blocks the migration of charge to a semiconductor device from proximate a through substrate via (TSV). In some embodiments, the IC comprises a substrate, an interconnect structure, the semiconductor device, the TSV, and the shield structure. The interconnect structure is on a frontside of the substrate and comprises a wire. The semiconductor device is on the frontside of the substrate, between the substrate and the interconnect structure. The TSV extends completely through the substrate, from a backside of the substrate to the wire, and comprises metal. The shield structure comprises a PN junction extending completely through the substrate and directly between the semiconductor device and the TSV.

Abstract: A semiconductor package structure includes a frontside redistribution layer, a first semiconductor die, a first capacitor, a conductive terminal, and a backside redistribution layer. The first semiconductor die is disposed over the frontside redistribution layer. The first capacitor is disposed over the frontside redistribution layer and electrically coupled to the first semiconductor die. The conductive terminal is disposed below the frontside redistribution layer and electrically coupled to the frontside redistribution layer. The backside redistribution layer is disposed over the first semiconductor die.

Abstract: An additive compound for dyeing an aluminum or aluminum alloy substrate after anodic oxidation to provide better uniformity in dyeing and hence a better finished appearance includes a main agent, an auxiliary agent, a pH stabilizer, and an antibacterial agent. The antibacterial agent includes at least one of sorbic acid, fluconazole, itraconazole, Artemisia argyi, benzyl alcohol, benzoic acid, salicylic acid, and boric acid. An additive solution and a dyeing method are also provided, the use of the compound also allows for a more rapid dyeing process.

Abstract: A method includes: receiving a composite substrate including a first region and a second region, the composite substrate including a semiconductor substrate and an insulator layer over the semiconductor substrate; forming a trench through the insulator layer, the trench exposing a surface of the semiconductor substrate in the first region; growing an initial epitaxial layer in the trench and over an upper surface of the second region; thickening the initial epitaxial layer to form an epitaxial layer; forming a transistor layer over the epitaxial layer, the transistor layer including a first transistor and a second transistor in the first region and the second region, respectively; and forming an interconnect layer over the transistor layer and electrically coupling the first transistor to the second transistor.

Abstract: Some implementations are directed to a wireless receiver. In some implementations, the wireless receiver may include a receiver body encompassing one or more antenna elements, a cover removably coupled to the receiver body, and a mounting bracket removably coupled to the receiver body. In some implementations, at least one of the one or more antenna elements, the cover, or the mounting bracket is movable with respect to the receiver body in order to align the wireless receiver with a signal path.

Abstract: A semiconductor structure includes a substrate, an isolation structure disposed in the substrate, and a hybrid structure disposed over the isolation structure. The hybrid structure is substantially conformal with respect to a profile of the isolation structure. The hybrid structure includes an oxide component, a nitride component surrounding the oxide component, and a first polysilicon component alongside the nitride component. The nitride component includes a first upper surface closed to the first polysilicon component, and a second upper surface distal to the first polysilicon component. The second upper surface is lower than the first upper surface.

Abstract: A BIOS setup environment configuration modification audit system includes a BIOS device that is included in a computing device and that is coupled to a component device in the computing device. The BIOS device enters a BIOS setup environment for the computing device and, while in the BIOS setup environment, detects component device configuration modification(s) to a configuration of the component device.

Abstract: An example electronic device includes a network communication interface to connect to a conference server, a central control device communication interface to connect to a local central control device, a microphone and a processor. The processor is to receive audio at the microphone and send the audio to the local central control device and to the conference server. The processor is to send the audio to the local central control device such that it is received by a nearby electronic device before the audio is received from the conference server by the nearby electronic device.

Abstract: A solid-state storage device is provided. The solid-state storage device is electrically connected to a host. The solid-state storage device includes a controller, a non-volatile memory, and a volatile memory. The non-volatile memory is electrically connected to the controller. The volatile memory is electrically connected to the controller. The volatile memory includes a submission queue and a completion queue. The controller is configured to fetch an access command from the host, and record the access command in the submission queue. The access command corresponds to a first logical address. The controller is configured to determine whether a first write command is in the submission queue to generate a determination result. The first write command corresponds to a second logical address identical to the first logical address. The controller is configured to decide a processing method of the access command according to the determination result.

Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.