Abstract: Approaches to selection of motion vector (“MV”) precision during video encoding are presented. These approaches can facilitate compression that is effective in terms of rate-distortion performance and/or computational efficiency. For example, a video encoder determines an MV precision for a unit of video from among multiple MV precisions, which include one or more fractional-sample MV precisions and integer-sample MV precision. The video encoder can identify a set of MV values having a fractional-sample MV precision, then select the MV precision for the unit based at least in part on prevalence of MV values (within the set) having a fractional part of zero. Or, the video encoder can perform rate-distortion analysis, where the rate-distortion analysis is biased towards the integer-sample MV precision. Or, the video encoder can collect information about the video and select the MV precision for the unit based at least in part on the collected information.

Abstract: A pixel driving circuit includes a first capacitor, a data input unit, a liquid crystal capacitor, a control unit and a driving unit. The first capacitor has a first terminal and a second terminal, wherein the first terminal is configured for receiving a first reference voltage. The data input unit is configured for inputting a data signal to the second terminal of the first capacitor according to a first scanning signal. The liquid crystal capacitor has a first terminal and a second terminal. The first terminal receives a first operating signal. The control unit is configured to control a voltage of the second terminal of the liquid crystal capacitor according to a second scanning signal. The driving unit is configured to control the voltage of the second terminal of the liquid crystal capacitor in response to the data input unit is disabled by the first scanning signal.

Abstract: A liquid crystal (LC) pixel circuit of a LC display panel includes a first, a second, a third and a fourth switches, a LC capacitor and a storage capacitor. A first and a control terminals of the first switch respectively receive a common voltage and a first gate signal. A first and a control terminals of the second switch respectively receive a data voltage and a second gate signal. The storage capacitor and the LC capacitor electrically connect between second terminals of the first and second switches. A first and a control terminals of the third switch respectively receive the common voltage and a third gate signal. A first and a control terminals of the fourth switch respectively receive a set voltage and a fourth gate signal. Second terminals of the third and the fourth switches respectively connect to the second terminals of the second and the first switches.

Abstract: A shift register circuit includes a driving unit outputting a first scan signal according to a first clock signal; a pull up unit outputting a driving voltage according to one of a second scan signal and a third scan signal; a pull down unit pulling down voltage of an output end according to a second clock signal; a pull down control unit controlling the voltage of the output end and a driving node according to the first clock signal; a reset unit pulling down the voltage level of the driving node according to a touch-enable signal; and an electric storage unit adjusting the voltage of the driving node according to a touch-stop signal. When the touch-enable signal is enabled, the clock signals and the touch-stop signal are disabled, and when the touch-stop signal is enabled, the clock signals and the touch-enable signal are disabled.

Abstract: Techniques and tools for conversion operations between modules in a scalable video encoding tool or scalable video decoding tool are described. For example, given reconstructed base layer video in a low resolution format (e.g., 4:2:0 video with 8 bits per sample) an encoding tool and decoding tool adaptively filter the reconstructed base layer video and upsample its sample values to a higher sample depth (e.g., 10 bits per sample). The tools also adaptively scale chroma samples to a higher chroma sampling rate (e.g., 4:2:2). The adaptive filtering and chroma scaling help reduce energy in inter-layer residual video by making the reconstructed base layer video closer to input video, which typically makes compression of the inter-layer residual video more efficient. The encoding tool also remaps sample values of the inter-layer residual video to adjust dynamic range before encoding, and the decoding tool performs inverse remapping after decoding.

Abstract: Techniques and tools for encoding enhancement layer video with quantization that varies spatially and/or between color channels are presented, along with corresponding decoding techniques and tools. For example, an encoding tool determines whether quantization varies spatially over a picture, and the tool also determines whether quantization varies between color channels in the picture. The tool signals quantization parameters for macroblocks in the picture in an encoded bit stream. In some implementations, to signal the quantization parameters, the tool predicts the quantization parameters, and the quantization parameters are signaled with reference to the predicted quantization parameters. A decoding tool receives the encoded bit stream, predicts the quantization parameters, and uses the signaled information to determine the quantization parameters for the macroblocks of the enhancement layer video. The decoding tool performs inverse quantization that can vary spatially and/or between color channels.

Abstract: An embodiment of the invention provides a thin-film transistor substrate, including: a substrate; a gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and covering the gate electrode; an active layer disposed on the gate insulating layer and above the gate electrode, wherein the active layer includes a metal oxide; a source electrode disposed on and electrically connecting to the active layer; a first insulating layer covering the source electrode; and a drain electrode disposed on and electrically connecting to the active layer, wherein the drain electrode includes a metal oxide layer.

Abstract: A pixel circuit includes a first capacitor whose two terminals are coupled to a first node and a ground end respectively, a first switch whose two terminals are coupled to a second node and a fourth node respectively, a liquid crystal, a second switch, a pull-up circuit, a pull-down circuit, a second capacitor and a third switch. The first switch is coupled to the first node and a first data input end. The liquid crystal is coupled to the second and a third node. The second switch is coupled to the second node and a second data input end. The pull-up circuit is coupled to the first node and the second node and a node of a high voltage. The pull-down circuit is coupled to the second node, the fourth node and the ground end. The third switch is coupled to the fourth node and the ground end.

Abstract: Disclosed herein are exemplary embodiments of innovations in the area of encoding pictures or portions of pictures (e.g., slices, coding tree units, or coding units) and determining whether and how certain filtering operation should be performed and flagged for performance by the decoder in the bitstream. In particular examples, various implementations for setting the sample adaptive offset (SAO) syntax elements in the H.265/HEVC standard are disclosed. Although these examples concern the H.265/HEVC standard and its SAO filter, the disclosed technology is more widely applicable to other video codecs that involve filtering operations (particularly multi-stage filtering operations) as part of their encoding and decoding processes.

Abstract: Techniques and tools for encoding enhancement layer video with quantization that varies spatially and/or between color channels are presented, along with corresponding decoding techniques and tools. For example, an encoding tool determines whether quantization varies spatially over a picture, and the tool also determines whether quantization varies between color channels in the picture. The tool signals quantization parameters for macroblocks in the picture in an encoded bit stream. In some implementations, to signal the quantization parameters, the tool predicts the quantization parameters, and the quantization parameters are signaled with reference to the predicted quantization parameters. A decoding tool receives the encoded bit stream, predicts the quantization parameters, and uses the signaled information to determine the quantization parameters for the macroblocks of the enhancement layer video. The decoding tool performs inverse quantization that can vary spatially and/or between color channels.

Abstract: Techniques and tools for conversion operations between modules in a scalable video encoding tool or scalable video decoding tool are described. For example, given reconstructed base layer video in a low resolution format (e.g., 4:2:0 video with 8 bits per sample) an encoding tool and decoding tool adaptively filter the reconstructed base layer video and upsample its sample values to a higher sample depth (e.g., 10 bits per sample). The tools also adaptively scale chroma samples to a higher chroma sampling rate (e.g., 4:2:2). The adaptive filtering and chroma scaling help reduce energy in inter-layer residual video by making the reconstructed base layer video closer to input video, which typically makes compression of the inter-layer residual video more efficient. The encoding tool also remaps sample values of the inter-layer residual video to adjust dynamic range before encoding, and the decoding tool performs inverse remapping after decoding.

Abstract: A liquid-crystal pixel unit includes a storage capacitor, a liquid-crystal capacitor, a data writing circuit, and a source-follower type output circuit. The storage capacitor includes a first electrode and a second electrode. The second electrode is configured to receive a first reference voltage. The liquid-crystal capacitor includes a third electrode and a fourth electrode. The fourth electrode is configured to receive a second reference voltage. The data writing circuit is electrically connected to the first electrode and the third electrode. The data writing circuit is controlled by a control signal to charge a data voltage into the storage capacitor and the liquid-crystal capacitor. The source-follower type output circuit includes an input terminal and an output terminal. The input terminal is electrically connected to the first electrode. The output terminal is electrically connected to the third electrode.

Abstract: A solar cell includes a semiconductor wafer, plural finger electrodes, at least one bus electrode, and at least one finger loop electrode. The semiconductor wafer has a light-receiving surface. The finger electrodes are arranged along a first direction and disposed on the light-receiving surface. The bus electrode is arranged along a second direction and disposed on the light-receiving surface, and the bus electrode is connected with the finger electrodes, in which the second direction is perpendicular to the first direction. The finger loop electrode is substantially arranged along the second direction and disposed on the light-receiving surface, and the finger loop electrode is connected to at least two of the finger electrodes, in which the finger loop electrode has a shape of non-square periodic wave.

Abstract: Disclosed herein are exemplary embodiments of innovations in the area of encoding pictures or portions of pictures and determining whether and how certain encoding operations should be performed and flagged for performance by the decoder in the bitstream. In particular examples, various implementations for selectively encoding picture portions (e.g., blocks) in a skip mode (e.g., as in the skip mode of the H.265/HEVC standard) are disclosed. Embodiments of the disclosed techniques can be used to improve encoder efficiency, decrease overall encoder resource usage, and/or improve encoder speed. Such embodiments can be used in encoder modes in which efficient, fast encoder performance is desired (e.g., during encoding of live events, such as video conferencing).

Abstract: Disclosed herein are exemplary embodiments of innovations in the area of encoding pictures or portions of pictures (e.g., slices, coding tree units, or coding units) and determining whether and how certain filtering operation should be performed and flagged for performance by the decoder in the bitstream. In particular examples, various implementations for selectively performing and selectively skipping aspects of sample adaptive offset (SAO) filtering as in the H.265/HEVC standard are disclosed. Although these examples concern the H.265/HEVC standard and its SAO filter, the disclosed technology is more widely applicable to other video codecs that involve filtering operations as part of their encoding and decoding processes.

Abstract: A display panel is provided. A display panel includes a plurality of pixels and a plurality of gate lines. The pixels include a first pixel, a second pixel and a third pixel. The gate lines include a first gate line, a second gate line and a third gate line. The first gate line drives the first pixel. The second gate line drives the second pixel. The third gate line drives the third pixel. The first gate line, the second gate line and the third gate line are disposed sequentially and driven at different time. The first pixel and the second pixel are arranged respectively at two opposite sides of the first gate line and the second gate line. The second pixel and the third pixel are arrange between the second gate line and the third gate line.

Abstract: Techniques and tools for video coding/decoding with motion resolution switching and sub-block transform coding/decoding are described. For example, a video encoder adaptively switches the resolution of motion estimation and compensation between quarter-pixel and half-pixel resolutions; a corresponding video decoder adaptively switches the resolution of motion compensation between quarter-pixel and half-pixel resolutions. For sub-block transform sizes, for example, a video encoder adaptively switches between 8x8, 8x4, and 4x8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding.

Abstract: The computational complexity of video encoding is reduced by selectively skipping certain evaluation stages when deciding whether to use inter-picture prediction or intra-picture prediction for a unit of a picture. For example, a video encoder receives a current picture of a video sequence and encodes the current picture. As part of the encoding, for a current unit (e.g., coding unit, macroblock) of the current picture, the encoder can skip time-consuming evaluation of intra-picture prediction modes for blocks of the current unit in situations in which motion compensation for the current unit is already expected to provide effective rate-distortion performance, and use of intra-picture prediction is unlikely to improve performance. In particular, evaluation of the intra-picture prediction modes for blocks of the current unit can be skipped when the current unit has little or no movement and intra-picture prediction has not been promising for the collocated unit in the previous picture.

Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.

Abstract: Techniques and tools for sub-block transform coding are described. For example, a video encoder adaptively switches between 8×8, 8×4, and 4×8 DCTs when encoding 8×8 prediction residual blocks; a corresponding video decoder switches between 8×8, 8×4, and 4×8 inverse DCTs during decoding. The video encoder may determine the transform sizes as well as switching levels (e.g., frame, macroblock, or block) in a closed loop evaluation of the different transform sizes and switching levels. The encoder and decoder may use different scan patterns for different transform sizes when scanning values from two-dimensional blocks into one-dimensional arrays, or vice versa. The encoder and decoder may use sub-block pattern codes to indicate the presence or absence of information for the sub-blocks of particular blocks.