Patents by Inventor Chih-Ming Chung

Chih-Ming Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200074265
    Abstract: An embodiment of the present invention provides a counting information updating method for a portable electronic device having a plurality of spheres connected with each other. The method includes: generating an angular velocity signal by a first sensor of the portable electronic device and generating an acceleration signal by a second sensor of the portable electronic device in response to a sphere moving operation; and estimating counting information corresponding to the sphere moving operation by using the angular velocity signal with an assistance of the acceleration signal.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 5, 2020
    Applicant: Acer Incorporated
    Inventors: Chih-Chieh Chien, Yi-Chun Chung, Pei-Wen Jung, Yen-Ming Hsu
  • Patent number: 10559717
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween, wherein the first semiconductor layer includes a surrounding exposed region not covered by the active layer, and the surrounding exposed region surrounds the active layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surrounding exposed region of the first semiconductor layer; an electrode layer formed on the first conductive region in the surrounding exposed region; an outside insulating layer covering a portion of the conductive layer and the electrode layer, and including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and a conductive substrate, w
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 11, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Teng Ko, Chao-Hsing Chen, Jia-Kuen Wang, Yen-Liang Kuo, Chih-Hao Chen, Wei-Jung Chung, Chih-Ming Wang, Wei-Chih Peng, Schang-Jing Hon, Yu-Yao Lin
  • Patent number: 10461223
    Abstract: A semiconductor device includes a semiconductor stack comprising a surface, and an electrode structure comprises an electrode pad formed on the surface, and the electrode structure further comprises a first extending electrode, a second extending electrode and a third extending electrode connecting to the electrode pad. The first extending electrode is closer to a periphery of the surface than the third extending electrode is, and the second extending electrode is between the first extending electrode and the third extending electrode. From a top view of the semiconductor device, the first extending electrode, the second extending electrode and the third extending electrode respectively include a first curve having a first angle ?1, a second curve having a second angle ?2 and a third curve having a third angle ?3, wherein ?3>?2>?1 .
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 29, 2019
    Assignee: Epistar Corporation
    Inventors: Yung-Fu Chang, Hsin-Chan Chung, Hung-Ta Cheng, Wen-Luh Liao, Shih-Chang Lee, Chih-Chiang Lu, Yi-Ming Chen, Yao-Ning Chan, Chun-Fu Tsai
  • Patent number: 10418002
    Abstract: Aspects of the disclosure provide a method for merging compressed access units according to compression rates and/or positions of the respective compressed access units. The method can include receiving a sequence of compressed access units corresponding to a sequence of raw access units partitioned from an image or a video frame and corresponding to a sequence of memory spaces in a frame buffer, determining a merged access unit including at least two consecutive compressed access units based on compression rates and/or positions of the sequence of compressed access units. The merged access unit is to be stored in the frame buffer with a reduced gap between the at least two consecutive compressed access units compared with storing the at least two consecutive compressed access units in corresponding memory spaces in the sequence of memory spaces.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 17, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ping Chao, Ting-An Lin, Tung-Hsing Wu, Kung-Tsun Yang, Wan-Yu Chen, Chuang-Chi Chiou, Ping-yao Wang, Wei-Gen Wu, Hsin-Hao Chung, Chih-Ming Wang, Han-Liang Chou, Chung Hsien Lee, Yung-Chang Chang, Chi-Cheng Ju
  • Patent number: 10323331
    Abstract: The present disclosure provides a valuable metal selectively adsorbing electrode, including: an electrode formed by a carbon-containing material; and a protein of a bacterium of genus Tepidimonas immobilized on the electrode formed by a carbon-containing material to form the valuable metal selectively adsorbing electrode, wherein the valuable metal includes gold, palladium, silver or indium.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Li-Ching Chung, Chia-Heng Yen, Teh-Ming Liang, Ren-Yang Horng, Min-Chao Chang, Hsin Shao, Po-I Liu, Chih-Hsiang Fang, Yin-Lung Han, Kai-Chun Fan
  • Patent number: 10301199
    Abstract: A method for electrochemically selectively removing ions using a composite electrode is provided. The composite electrode includes a composite having a carbon support and an inorganic material immobilized on the carbon support.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 28, 2019
    Assignee: Industrial Technology Research Institute
    Inventors: Li-Ching Chung, Teh-Ming Liang, Ren-Yang Horng, Hsin Shao, Po-I Liu, Min-Chao Chang, Chia-Heng Yen, Chih-Hsiang Fang
  • Patent number: 9754924
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: September 5, 2017
    Assignee: Apple Inc.
    Inventor: Chih-Ming Chung
  • Patent number: 9601464
    Abstract: In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include a first package, a second package, and a shield. The first package may include a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface substantially opposite the third surface, and a second die. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The shield may be applied to the fourth surface of the semiconductor device package assembly. In some embodiments, the shield may transfer, during use, heat from the first die.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 21, 2017
    Assignee: Apple Inc.
    Inventor: Chih-Ming Chung
  • Patent number: 9583472
    Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 28, 2017
    Assignee: Apple Inc.
    Inventors: Chih-Ming Chung, Jun Zhai, Yizhang Yang
  • Patent number: 9452591
    Abstract: A tempered glass screen protector includes a substrate structure, a protection structure, and an adhesion structure. The substrate structure has a transparent portion and a non-planar decorative portion extended from the transparent portion. The protection structure includes a first transparent adhesive layer disposed on the bottom surface of the transparent portion and a transparent protective layer disposed on the first transparent adhesive layer. The adhesion structure includes a first adhesive layer disposed on the bottom surface of the non-planar decorative portion, a base layer disposed on the first adhesive layer, and a second adhesive layer disposed on the base layer. The thickness of the protection structure is smaller than the thickness of the adhesion structure, so that there is no any watermark or Newton ring formed between the transparent protective layer and the display area of the portable electronic device when pressing the transparent portion.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: September 27, 2016
    Assignee: G-TECH OPTOELECTRONICS CORPORATION
    Inventors: Chih-Ming Chung, Hsing Chiao Lin, Yuh-Chang Lan
  • Publication number: 20160268236
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Application
    Filed: May 25, 2016
    Publication date: September 15, 2016
    Inventor: Chih-Ming Chung
  • Publication number: 20160260695
    Abstract: Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), stacked die between the first and second RDLs, and conductive pillars extending between the RDLs. A molding compound may encapsulate the stacked die and conductive pillars between the first and second RDLs.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: Chih-Ming Chung, Jun Zhai, Yizhang Yang
  • Patent number: 9379097
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: June 28, 2016
    Assignee: Apple Inc.
    Inventor: Chih-Ming Chung
  • Publication number: 20160107421
    Abstract: A tempered glass screen protector includes a substrate structure, a protection structure, and an adhesion structure. The substrate structure has a transparent portion and a non-planar decorative portion extended from the transparent portion. The protection structure includes a first transparent adhesive layer disposed on the bottom surface of the transparent portion and a transparent protective layer disposed on the first transparent adhesive layer. The adhesion structure includes a first adhesive layer disposed on the bottom surface of the non-planar decorative portion, a base layer disposed on the first adhesive layer, and a second adhesive layer disposed on the base layer. The thickness of the protection structure is smaller than the thickness of the adhesion structure, so that there is no any watermark or Newton ring formed between the transparent protective layer and the display area of the portable electronic device when pressing the transparent portion.
    Type: Application
    Filed: March 23, 2015
    Publication date: April 21, 2016
    Inventors: CHIH-MING CHUNG, HSING CHIAO LIN, YUH-CHANG LAN
  • Patent number: 9263426
    Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: February 16, 2016
    Assignee: Apple Inc.
    Inventors: Jie-Hua Zhao, Yizhang Yang, Jun Zhai, Chih-Ming Chung
  • Publication number: 20160027766
    Abstract: Package on package structures and manners of formation are described. In an embodiment, an array of trenches is formed partially through a fan-out substrate. In an embodiment, a plurality of laterally separate locations thermal interface material is dispensed onto an array of embedded bottom die. In an embodiment a thermal compression tool including an array of cavities corresponding to an array of top packages is brought into contact with the array of top packages and underlying fan-out substrate during PoP joint formation. The fan-out substrate may be secured to a vacuum chuck during several processing operations.
    Type: Application
    Filed: September 23, 2014
    Publication date: January 28, 2016
    Inventor: Chih-Ming Chung
  • Publication number: 20160013155
    Abstract: In some embodiments, a semiconductor device package may include a semiconductor device package on package assembly. The package on package assembly may include a first package, a second package, and a shield. The first package may include a first surface, a second surface substantially opposite the first surface, a first die, and a first set of electrical conductors coupled to the first surface and configured to electrically connect the package on package assembly. The second package may include a third surface and a fourth surface substantially opposite the third surface, and a second die. The third surface may be coupled to the second surface. The first package may be electrically coupled to the second package. The shield may be applied to the fourth surface of the semiconductor device package assembly. In some embodiments, the shield may transfer, during use, heat from the first die.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventor: Chih-Ming Chung
  • Publication number: 20150255366
    Abstract: In some embodiments, a system and/or method may include forming a semiconductor device package assembly. The method may include forming a substrate including a first surface and a second surface substantially opposite the first surface. The substrate may include an opening in the second surface. The first surface may include a first set of electrical conductors. The method may include positioning a first die in the opening. The first die may include a second set of electrical conductors. The method may include forming a third set of electrical conductors on a second die. The third set of conductors may include a first width and a first height. The method may include forming a fourth set of electrical conductors on the second die. The fourth set of conductors may include a second width and a second height. The second width may be less than the first width. The second height may be greater than the first height.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: Apple Inc.
    Inventor: Chih-Ming Chung
  • Patent number: 9067813
    Abstract: A forming mold made from a polyporous refractory material is provided for forming a glass piece. The forming mold includes an outer surface and a plurality of forming structures provided on the outer surface. Each of the forming structures includes a forming surface matching with a shape of the glass piece. The forming mold is structured and arranged to be pumped down from the outer surface to generated an absorption force on molten glass material provided at the at least one forming surface for sucking the molten glass material on the forming structure to form the glass piece.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: June 30, 2015
    Assignee: G-TECH Optoelectronics Corporation
    Inventors: Chih-Ming Chung, Jung-Pin Hsu, Tai-Hua Lee, Chao-Hsien Lee
  • Publication number: 20150118795
    Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.
    Type: Application
    Filed: January 9, 2015
    Publication date: April 30, 2015
    Inventors: Jie-Hua Zhao, Yizhang Yang, Jun Zhai, Chih-Ming Chung