Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: A multi-chip package structure including a carrier, a first chip having an active surface and a rear surface, multiple bumps, a second chip, multiple first bonding wires, a package unit disposed above the first chip, a spacer disposed between the package unit and the first chip, multiple second bonding wires, and an encapsulant is provided. The bumps are disposed between the active surface and the carrier to electrically connect the first chip and the carrier. The second chip is disposed on the rear surface of the first chip. The first bonding wires electrically connect the second chip and the carrier. The second bonding wires electrically connect the package unit and the carrier. The encapsulant is disposed on the carrier to encapsulate the first chip, the second chip, at least a portion of the package unit, the bumps, the spacer, the first bonding wires and the second bonding wires.

Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.

Abstract: The invention achieves the above-identified object by providing a packaging, comprising steps of: (a) providing an integrated circuit unit having an active surface, a plurality of bumps disposed thereon; (b) providing a substrate having a first surface and a second surface, a plurality of pads disposed on the first surface, a metal layer formed on the second surface; (c) forming an integrated circuit assembly by connecting the bumps and pads; and (d) forming a plurality of metallic pieces by etching the metal layer.

Abstract: A multi-chip package substrate for both flip-chip bumping and wire-bonding applications comprises a substrate body having a top surface and a bottom surface. A plurality of bumping pads and a plurality of wire-bonding pads are formed on the top surface. The bumping pads are disposed on the top surface of the substrate body and a pre-solder material is formed on the bumped pads. The wire-bonding pads are disposed on the top surface of the substrate body and a Ni/Au layer is formed on the wire-bonding pads. In order to avoid the bumping pads and the wire-bonding pads from oxidation during packaging processes. The pre-solder material fully covers the bumping pads to avoid the Au intermetallics generated in a plurality of bumps on a bumped chip during packaging processes. The reliability of the multi-chip stacked package for both flip-chip bumping and wire-bonding applications will be greatly improved.

Abstract: The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a plurality of bumps in the openings, wherein the height of the bumps is smaller than the depth of the openings; (e) providing a second element having a plurality of pre-solders; and (f) bonding the first surface onto the second element, so that the pre-solders are disposed in the openings and in contact with the bumps. As a result, the self-alignment between the pre-solders and the bumps can avoid the shift between the first element and the second element.

Abstract: The present invention relates to a method for flip chip bonding by utilizing an interposer with embedded bumps. The method comprises (a) providing a first element having a first surface; (b) forming an interposer onto the first surface; (c) forming a plurality of openings on the interposer; (d) forming a plurality of bumps in the openings, wherein the height of the bumps is smaller than the depth of the openings; (e) providing a second element having a plurality of pre-solders; and (f) bonding the first surface onto the second element, so that the pre-solders are disposed in the openings and in contact with the bumps. As a result, the self-alignment between the pre-solders and the bumps can avoid the shift between the first element and the second element.

Abstract: A package substrate for carrying a chip with a plurality of bumps thereon is provided. The package substrate includes a first substrate, and an interposer. The first substrate has a first circuit layer disposed on a surface thereof. The interposer includes a second substrate and a second circuit layer formed thereon. The second circuit layer comprises a plurality of bonding pads and traces. The traces are electrically connected to the corresponding bonding pads. Furthermore, the bonding pads are used for being connected to the bumps. The second circuit layer of the interposer is physically and electrically connected to the first circuit layer of the first substrate, and the second substrate and the first substrate are made of different materials.

Abstract: A process for fabricating a chip package structure with the following steps is provided. First, a chip having an active surface is provided. A plurality of solder bumps is disposed on the active surface. Then, a polymer material including flux is placed on the surface of the solder bumps by a dipping process. The chip is disposed on a carrier such that the carrier is in contact with the solder bumps. A reflow process is carried out so that the chip and the carrier are electrically connected through the solder bumps and a plurality of supporting structures made from the polymer material are formed around the junctions between the solder bumps and the carrier. The supporting structures enhance the endurance of the solder bumps to thermal stress and reduce damage due to fatigue.

Abstract: The present invention relates to a multi-chip module package structure including a substrate with at least a slot, at least a first and a second chips and a molding compound. The first chip is larger than the second chip. The two chips are respectively disposed on two opposite surfaces of the substrate, while the slot exposes the bonding pads of the first chip. The bonding pads of the first chip are electrically connected to the top surface of the substrate by wire bonding. The second chip is electrically attached to the substrate by flip chip bonding or wire bonding. The molding compound at least covers the first and second chips and a portion of the substrate.

Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, some buffer material and some encapsulation is provided. The substrate has a first surface and a corresponding second surface. The chip has an active surface and a back surface. The bumps are disposed between the active surface of the chip and the first surface of the substrate. The buffer material is disposed on the back surface of the chip. The encapsulation is disposed over the first surface of the substrate to enclose the chip and the buffer material.

Abstract: A stacked flip-chip package comprises a substrate having an opening, a back-to-face chip module, and an encapsulant. The back-to-face chip module is attached to the substrate and encapsulated by the encapsulant. The back-to-face chip module includes a first chip and a second chip. The first chip has a first active surface and a first back surface. Redistributed traces are formed on the first back surface. The second chip is flip-chip mounted on the first back surface of the first chip and electrically connected to the redistributed traces. A plurality of bumps connect the redistributed traces to the top surface of the substrate. Thus the second chip can be accommodated inside the opening and the redistributed traces are electrically connected to the second chip and the substrate so as to achieve fine pitch flip-chip mounting and improve the electrical performance and heat dissipation efficiency for the back-to-face chip module.

Abstract: A manufacturing method of a bumped wafer package mainly comprises providing a photosensitive adhesion layer over the active surface of the wafer, forming a plurality of openings in the photosensitive adhesion layer to expose the bonding pads on the active surface of the wafer through an exposure and development processes, forming a plurality of bumps in the openings through printing process and reflowing the bumps with keeping the photosensitive adhesion layer partially cured. In such a manner, the bumps can be well encapsulated in the photosensitive adhesion layer without gaps between the bumps and the photosensitive adhesion layer.