Abstract: A method of image format conversion and remote control device using the same. Addition terms for a first layer are derived from an image conversion table. Every two addition terms are assigned to an addition group, obtaining a plurality of addition groups. The two addition terms of each addition group are added by using an adder to obtain addition terms for next layer thereafter. The bit number of the adder is equivalent to that of one addition term comprising the maximum bit number in every addition group. Finally, the addition process is repeated to obtain the operation result.

Abstract: The invention discloses a method for detecting resolution and a device for the same. Resolution data entries corresponding to a display device are classified into a plurality of first and second counting groups according to first and second timing counts respectively. Image signals from a video source are detected, acquiring a first counting group and a second counting group according to the resolution data entries. When the only resolution data entry corresponding to the image signals is included in the first counting group, the image signals corresponding to the resolution data entry is displayed. When a first resolution data entry and at least one second resolution data entry are included in the first counting group and only the first resolution data entry is included in the second counting group, the image signals corresponding to the first resolution data entry is displayed.

Abstract: A bus interface extender and a method thereof, is utilized between a bus arbitrator (e.g. a PCI bus arbitrator) and at least one PCI device, such that the amount of bus devices electrically coupled with the bus arbitrator can be increased without modifying architecture of the bus arbitrator. The bus arbitrator has a priority decision module, a grant decision module, and a bus signal processing module. The priority decision module determines a priority sequence for each of the bus devices. The grant decision module grants access of the proper bus device to the system bus, according to request status and priority thereof. The bus signal processing module manages transmission of request/grant signals among the PCI devices and the bus arbitrator, according to decision of the grant decision module.

Abstract: The present invention provides a safe power-off system and method thereof used for an electrical system. When a user pushes a power-off button of the electrical system, the safe power-off system will receive a power-off signal generated by the power supply apparatus and therefore generate a corresponding interrupt signal to the main system to perform a preparation program having a system power-off preparation procedure. After the main system has completed the power-off preparation procedure, it will acknowledge the safe power-off apparatus that the power can be cut off and subsequently proceeds to cut off the power connection between the system and the power supply apparatus.

Abstract: A system bus controller for a computer system and a related method are introduced. The computer system has at least a bus and a bus master electrically connected to the bus. The system bus controller includes a bus slave interface, a master queue, a bus master interface, a queue entries executor and a master queue management unit. Initially, any entry command transmitted over the bus by the bus master will be sequentially queued in a memory. Then, a corresponding acknowledge signal to release access of the bus is generated by the queue management unit. Then, the queued entry commands are sequentially executed to generate corresponding results, which will be caught by the bus master in an active or passive manner.

Abstract: A system and method for actively booting a computer system, according to the present invention, are capable of controlling a CPU of the computer system to selectively access boot codes from either an XIP type or non-XIP type memory devices attached in the computer system to initiate an operating system of the computer system.

Abstract: A controller for digital asynchronized half-duplex serial transmission gate. The controller includes a RS232/TTL interface for transforming a received RS232 signal into a TTL signal, a RS484/TTL interface for transforming the TTL signal into a RS485 signal, having a Rx/Tx control terminal, and a phase processing unit for receiving the TTL signal to generate a Rx/Tx control signal input to the Rx/Tx control terminal, wherein the Rx/Tx control signal is derived by inverting and delaying the TTL signal for a time interval.

Abstract: A planar filter includes a ground plane underlying a dielectric substrate, and input and output resonators provided on the dielectric substrate. Each of the input and output resonators has a feed point provided on a transmission line conductor that is divided by the feed point into a long transmission line segment and a short transmission line segment, each which has an open end. A first signal path is defined from a first feed point provided on the input resonator to a second feed point provided on the output resonator. A second signal path is defined from the second feed point to the first feed point. A phase difference between the first and second signal paths is substantially equal to zero degree when the filter operates at a central operating frequency thereof.