Abstract: A semiconductor structure comprising a first layer, a metal layer and a second layer is disclosed. The first layer comprises a recessed surface. The metal layer is above a portion of the recessed surface. The second layer is above the metal layer and confined by the recessed surface. The second layer comprises a top surface, a first lateral side and a second lateral side. The etch rate of an etchant with respect to the metal layer is greater than the etch rate of the etchant with respect to the second layer. The thickness of the second layer in the middle of the second layer is less than the thickness of the second layer at the first lateral side or the second lateral side. A method of forming a semiconductor structure is disclosed.

Abstract: A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region formed in the substrate. The semiconductor device further includes an impurity diffusion stop layer formed in a recess of the substrate between the source region and the drain region, wherein the impurity diffusion stop layer covers bottom and sidewalls of the recess. The semiconductor device further includes a channel layer formed over the impurity diffusion stop layer and in the recess, and a gate stack formed over the channel layer.

Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.

Abstract: A method for forming a semiconductor device is provided. The method includes forming an isolation structure in a semiconductor substrate, and the isolation structure surrounds an active region of the semiconductor substrate. The method also includes forming a gate over the semiconductor substrate, and the gate is across the active region and extends onto the isolation structure. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, the end portions are over the isolation structure. The method includes forming a support film over the isolation structure, and the support film is a continuous film which continuously covers the isolation structure and at least one end portion of the gate.

Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.

Abstract: Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another.

Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a semiconductor substrate. The method also includes performing a hydrogen-containing plasma treatment on the metal gate stack to modify a surface of the metal gate stack. The hydrogen-containing plasma treatment includes exciting a gas mixture including a first hydrogen-containing gas and a second hydrogen-containing gas to generate a hydrogen-containing plasma.

Abstract: A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.

Abstract: The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.

Abstract: A method of manufacturing a semiconductor device includes receiving a FinFET precursor including a fin structure formed between some isolation regions, and a gate structure formed over a portion of the fin structure; removing a top portion of the fin structure on either side of the gate structure; growing a semiconductive layer on top of a remaining portion of the fin structure such that a plurality of corners is formed over the fin structure; forming a capping layer over the semiconductive layer; performing an annealing process on the FinFET precursor to form a plurality of dislocations proximate to the corners; and removing the capping layer.

Abstract: A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (PMID) layer and a composite layer is disclosed. The PMID layer is above the substrate. The composite layer is between the substrate and the PMID layer. The composite layer comprises a first sublayer and a second sublayer. The first sublayer and the second sublayer are stacked. The bandgap of the second sublayer is larger than the bandgap of the first sublayer. The etch rate of an etchant with respect to the first sublayer is lower than the etch rate of the etchant with respect to the substrate and the PMID layer. Other semiconductor structures are also disclosed.

Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.

Abstract: The present disclosure relates to a method of forming a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the method is performed by selectively etching a semiconductor substrate to form a recess along a top surface of the semiconductor substrate. A sandwich film stack having a plurality of nested layers is formed within the recess. At least two of the nested layers include different materials that improve different aspects of the performance of the transistor device. A gate structure is formed over the sandwich film stack. The gate structure controls the flow of charge carriers in a channel region having the sandwich film stack, which is laterally positioned between a source region and a drain region disposed within the semiconductor substrate.