Patents by Inventor Chih-Mu Huang
Chih-Mu Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150241768Abstract: A semiconductor device includes a first material formed on a substrate. The first material includes a first alignment mark. The first alignment mark includes alignment lines in at least three directions. The semiconductor device further includes a second material comprising a second alignment mark. The second alignment mark corresponds to the first alignment mark such that when the second alignment mark is aligned with the first alignment mark, the second material is aligned with the first material.Type: ApplicationFiled: February 27, 2014Publication date: August 27, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Shang Hsiao, I-I Cheng, Jia-Ming Huang, Jen-Pan Wang, Ling-Sung Wang, Chih-Mu Huang
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Publication number: 20150206946Abstract: A semiconductor device includes a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; and an interconnect plug on the doped region. The raised source/drain region includes a top surface being elevated from a surface of the substrate; and a doped region exposed on the top surface. The doped region includes a dopant concentration greater than any other portions of the raised source/drain region. A bottommost portion of the interconnect plug includes a width approximate to a width of the doped region.Type: ApplicationFiled: October 31, 2014Publication date: July 23, 2015Inventors: I-CHIH CHEN, FU-TSUN TSAI, YUNG-FA LEE, KO-MIN LIN, CHIH-MU HUANG, YING-LANG WANG
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Publication number: 20150206945Abstract: A semiconductor device includes a metal oxide semiconductor device disposed over a substrate and an interconnect plug. The metal oxide semiconductor device includes a gate structure located on the substrate and a raised source/drain region disposed adjacent to the gate structure. The raised source/drain region includes a top surface above a surface of the substrate by a distance. The interconnect plug connects to the raised source/drain region. The interconnect plug includes a doped region contacting the top surface of the raised source/drain region, a metal silicide region located on the doped region, and a metal region located on the metal silicide region.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: I-CHIH CHEN, CHIH-MU HUANG, LING-SUNG WANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG
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Publication number: 20150200299Abstract: A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate; a source/drain region having a first dopant in the substrate; a barrier layer having a second dopant formed around the source/drain region in the substrate. When a semiconductor device is scaled down, the doped profile in source/drain regions might affect the threshold voltage uniformity, the provided semiconductor device may improve the threshold voltage uniformity by the barrier layer to control the doped profile.Type: ApplicationFiled: March 25, 2014Publication date: July 16, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Chih CHEN, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
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Publication number: 20150137247Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-CHIH CHEN, YING-LANG WANG, CHIH-MU HUANG, YING-HAO CHEN, WEN-CHANG KUO, JUNG-CHI JENG
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Publication number: 20150129940Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. The semiconductor device also includes an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device includes a gate over the semiconductor substrate. The gate has an intermediate portion over the active region and two end portions connected to the intermediate portion. Each of the end portions has a first gate length longer than a second gate length of the intermediate portion and is located over the isolation structure.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
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Publication number: 20150129987Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate. The semiconductor device also includes a gate over the semiconductor substrate, and the gate has an intermediate portion over the active region and two end portions connected to the intermediate portion, and the end portions are over the isolation structure. The semiconductor device further includes a support film over the isolation structure and covering the isolation structure and at least one of the end portions of the gate. The support film exposes the active region and the intermediate portion of the gate.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi JENG, I-Chih CHEN, Wen-Chang KUO, Ying-Hao CHEN, Ru-Shang HSIAO, Chih-Mu HUANG
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Publication number: 20150132919Abstract: In a method for manufacturing a dual shallow trench isolation structure, a substrate is provided, and a mask layer is formed on the substrate. The mask layer is patterned by using a photomask to form at least one first hole and at least one second hole in the mask layer, in which a depth of the at least one first hole is different from a depth of the at least one second hole. The mask layer and the substrate are etched to form at least one first trench having a first depth and at least one second trench having a second depth, in which the first depth is different from the second depth. The remaining mask layer is removed. A first isolation layer and A second isolation layer are respectively formed in the at least one first trench and the at least one second trench.Type: ApplicationFiled: November 14, 2013Publication date: May 14, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Fu-Cheng CHANG, Chai-Der YEN, Fu-Tsun TSAI, Chi-Cherng JENG, Chih-Mu HUANG
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Publication number: 20150044810Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.Type: ApplicationFiled: October 28, 2014Publication date: February 12, 2015Inventors: I-I Cheng, Chih-Mu Huang, Pin Chia Su, Chi-Cherng Jeng, Volume Chien, Chih-Kang Chao
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Publication number: 20140367820Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.Type: ApplicationFiled: August 26, 2014Publication date: December 18, 2014Inventors: Che-Min Lin, Volume Chien, Chih-Kang Chao, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
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Patent number: 8884390Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.Type: GrantFiled: January 30, 2013Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-I Cheng, Chih-Kang Chao, Volume Chien, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
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Publication number: 20140268609Abstract: Among other things, one or more support structures for integrated circuitry and techniques for forming such support structures are provided. A support structure comprises one or more trench structures, such as a first trench structure and a second trench structure formed around a periphery of integrated circuitry. In some embodiments, one or more trench structures are formed according to partial substrate etching, such that respective trench structures are formed into a region of a substrate. In some embodiments, one or more trench structures are formed according to discontinued substrate etching, such that respective trench structures comprise one or more trench portions separated by separation regions of the substrate. The support structure mitigates stress energy from reaching the integrated circuitry, and facilitates process-induced charge release from the integrated circuitry.Type: ApplicationFiled: May 14, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Volume Chien, Yun-Wei Cheng, I-l Cheng, Shiu-Ko JangJiang, Chi-Cherng Jeng, Chih-Mu Huang
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Publication number: 20140264696Abstract: Among other things, one or more image sensors and techniques for forming such image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises a calibration region configured to detect a color level for image reproduction, such as a black calibration region configured to detect a black level for an image detected by the photodiode array. The image sensor comprises a dielectric film that is formed over the photodiode array and the calibration region. The dielectric film is configured to balance stress between the photodiode and the calibration region in order to improve accuracy of the calibration region.Type: ApplicationFiled: March 21, 2014Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Volume Chien, Che-Min Lin, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
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Patent number: 8816415Abstract: A photodiode structure includes a photodiode and a concave reflector disposed below the photodiode. The concave reflector is arranged to reflect incident light from above back toward the photodiode.Type: GrantFiled: January 16, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Min Lin, Volume Chien, Chih-Kang Chao, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
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Publication number: 20140211057Abstract: An embodiment image sensor includes a pixel region spaced apart from a black level control (BLC) region by a buffer region. In an embodiment, a light shield is disposed over the BLC region and extends into the buffer region. In an embodiment, the buffer region includes an array of dummy pixels. Such embodiments effectively reduce light cross talk at the edge of the BLC region, which permits more accurate black level calibration. Thus, the image sensor is capable of producing higher quality images.Type: ApplicationFiled: July 17, 2013Publication date: July 31, 2014Inventors: Jung-Liang Chien, Yun-Wei Cheng, Che-Min Lin, Shiu-Ko JangJian, Chi-Cherng Jeng, Chih-Mu Huang
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Publication number: 20140210029Abstract: A die includes a first plurality of edges, and a semiconductor substrate in the die. The semiconductor substrate includes a first portion including a second plurality of edges misaligned with respective ones of the first plurality of edges. The semiconductor substrate further includes a second portion extending from one of the second plurality of edges to one of the first plurality of edges of the die. The second portion includes a first end connected to the one of the second plurality of edges, and a second end having an edge aligned to the one of the first plurality of edges of the die.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-I Cheng, Chih-Kang Chao, Volume Chien, Chi-Cherng Jeng, Pin Chia Su, Chih-Mu Huang
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Patent number: 7368775Abstract: A single transistor planar DRAM memory cell with improved charge retention and reduced current leakage and a method for forming the same, the method including providing a semiconductor substrate; forming a gate dielectric on the semiconductor substrate; forming a pass transistor structure adjacent a storage capacitor structure on the gate dielectric; forming sidewall spacer dielectric portions adjacent either side of the pass transistor to include covering a space between the pass transistor and the storage capacitor; forming a photoresist mask portion covering the pass transistor and exposing the storage capacitor; and, carrying out a P type ion implantation and drive in process to form a P doped channel region in the semiconductor substrate underlying the storage capacitor.Type: GrantFiled: July 31, 2004Date of Patent: May 6, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Mu Huang, Mingchu King, Yun Chang
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Patent number: 7176081Abstract: A novel, low-temperature metal deposition method which is suitable for depositing a metal film on a substrate, such as in the fabrication of metal-insulator-metal (MIM) capacitors, is disclosed. The method includes depositing a metal film on a substrate using a deposition temperature of less than typically about 270 degrees C. The resulting metal film is characterized by enhanced thickness uniformity and reduced grain agglomeration which otherwise tends to reduce the operational integrity of a capacitor or other device of which the metal film is a part. Furthermore, the metal film is characterized by intrinsic breakdown voltage (Vbd) improvement.Type: GrantFiled: May 20, 2004Date of Patent: February 13, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Fu Chang, Yen-Hsiu Chen, Hung-Jen Lin, Ming-Chu King, Ching-Hwanq Su, Chih-Mu Huang, Yun Chang
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Publication number: 20060240624Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.Type: ApplicationFiled: June 22, 2006Publication date: October 26, 2006Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Mu Huang, Mingchu King, Yun Chang
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Patent number: 7087483Abstract: A single transistor planar RAM memory cell with improved charge retention and a method for forming the same, the method including providing forming a pass transistor structure adjacent a storage capacitor structure separated by a predetermined distance; carrying out a first ion implantation process to form first and second doped regions adjacent either side of the pass transistor structure, the first doped region defined by the predetermined distance; depositing a spacer dielectric layer; etching back the spacer dielectric layer to leave an unetched spacer dielectric layer portion overlying the first doped region while forming a sidewall spacer of a predetermined width overlying a first portion of the second doped region; and, carrying out a second ion implantation process to form a relatively higher dopant concentration in a second portion of the second doped region.Type: GrantFiled: November 25, 2003Date of Patent: August 8, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Mu Huang, Mingchu King, Yun Chang