Patents by Inventor Chih-Nan Wu

Chih-Nan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210043670
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Publication number: 20200350244
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 10818716
    Abstract: An image sensor device includes a substrate, a pixel circuit, a dielectric structure, a photo sensitive element, a grid, and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The pixel circuit is disposed on the first side of the substrate. The dielectric structure is disposed on the second side of the substrate. The photo sensitive element is disposed between the pixel circuit and the dielectric structure. The grid is disposed on the dielectric structure. The convex dielectric lens is disposed on the dielectric structure. The convex dielectric lens has a convex side. A topmost of the convex side is above an interface between the dielectric structure and the grid.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Patent number: 10797176
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Publication number: 20200313051
    Abstract: The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 1, 2020
    Inventors: Cheng-Nan HAN, Tsung-Xian LEE, Min-Hsun HSIEH, Hung-Hsuan CHEN, Hsin-Mao LIU, Hsing-Chao CHEN, Ching-San TAO, Chih-Peng NI, Tzer- Perng CHEN, Jen-Chau WU
  • Publication number: 20200294821
    Abstract: A post CMP cleaning apparatus is provided. The post CMP cleaning apparatus includes a cleaning stage. The post CMP cleaning apparatus also includes a rotating platen disposed in the cleaning stage, and the rotating platen is configured to hold and rotate a semiconductor wafer. The post CMP cleaning apparatus further includes a vibrating device disposed over the rotating platen. The post CMP cleaning apparatus further includes a solution delivery module disposed near the vibrating device and configured to deliver a cleaning fluid to the semiconductor wafer. The vibrating device is configured to provide the cleaning fluid with a specific frequency which is at least greater than 100 MHz while the rotating platen is rotating the semiconductor wafer, so that particles on the semiconductor wafer are removed by the cleaning fluid.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Chen-Hao WU, Chu-An LEE, Chun-Hung LIAO, Shen-Nan LEE, Teng-Chun TSAI, Huang-Lin CHAO, Chih-Hung CHEN
  • Publication number: 20200286572
    Abstract: A gate driving circuit comprises a plurality of shift registers coupled in serial. An nth shift register includes a driving circuit, a pull-up circuit and a first auxiliary voltage regulator circuit. The driving circuit is electrically coupled to an output node and a first node. The driving circuit is configured to receive a clock signal and output a gate signal according to the clock signal. The pull-up circuit is electrically coupled to the driving circuit. The first auxiliary voltage regulator circuit is electrically coupled to the pull-up circuit and a second node. The first auxiliary voltage regulator circuit is configured to receive a control signal and the second node corresponding to a second voltage.
    Type: Application
    Filed: November 11, 2019
    Publication date: September 10, 2020
    Inventors: Er-Lang DENG, Yuan-Nan CHIU, Chih-Yuan WU, Yu-Lin HUANG, I-Sheng LIN, Kuo-Ting YANG
  • Patent number: 10720386
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 10686106
    Abstract: The disclosure discloses an optoelectronic element comprising: an optoelectronic unit comprising a first metal layer, a second metal layer, and an outermost lateral surface; an insulating layer having a first portion overlapping the optoelectronic unit and extending beyond the lateral surface, and a second portion separated from the first portion in a cross-sectional view; and a first conductive layer formed on the insulating layer.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: June 16, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Nan Han, Tsung-Xian Lee, Min-Hsun Hsieh, Hung-Hsuan Chen, Hsin-Mao Liu, Hsing-Chao Chen, Ching-San Tao, Chih-Peng Ni, Tzer-Perng Chen, Jen-Chau Wu
  • Publication number: 20200098883
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20200066911
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10529898
    Abstract: An optoelectronic element includes an optoelectronic unit, a first metal layer, a second metal layer, a conductive layer and a transparent structure. The optoelectronic unit has a central line in a top view, a top surface, and a bottom surface. The second metal layer is formed on the top surface, and has an extension portion crossing over the central line and extending to the first metal layer. The conductive layer covers the first metal layer and the extension portion. The transparent structure covers the bottom surface without covering the top surface.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: January 7, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Cheng-Nan Han, Tsung-Xian Lee, Min-Hsun Hsieh, Hung-Hsuan Chen, Hsin-Mao Liu, Hsing-Chao Chen, Ching San Tao, Chih-Peng Ni, Tzer-Perng Chen, Jen-Chau Wu, Masafumi Sano, Chih-Ming Wang
  • Patent number: 10522640
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20190348458
    Abstract: An image sensor device includes a substrate, a pixel circuit, a dielectric structure, a photo sensitive element, a grid, and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The pixel circuit is disposed on the first side of the substrate. The dielectric structure is disposed on the second side of the substrate. The photo sensitive element is disposed between the pixel circuit and the dielectric structure. The grid is disposed on the dielectric structure. The convex dielectric lens is disposed on the dielectric structure. The convex dielectric lens has a convex side. A topmost of the convex side is above an interface between the dielectric structure and the grid.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Patent number: 10367021
    Abstract: An image sensor device includes a substrate, a photo sensitive element, a first dielectric structure and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The photo sensitive element is formed on the first side of the substrate for receiving incident light transmitted through the substrate. The first dielectric structure is formed on the second side of the substrate. At least one portion of the convex dielectric lens is located in the first dielectric structure. The convex dielectric lens has a convex side oriented toward the incident light and a planar side oriented toward the photo sensitive element.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Publication number: 20190058063
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Publication number: 20190043805
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: October 1, 2018
    Publication date: February 7, 2019
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 10109741
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10090242
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: October 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20180226485
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 9, 2018
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin