Patents by Inventor Chih-Nan Wu

Chih-Nan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12272708
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.
    Type: Grant
    Filed: December 5, 2022
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Patent number: 11942419
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20230411204
    Abstract: A semiconductor device and a manufacturing method is provided. The semiconductor device includes a substrate, a shallow trench isolation structure, a dielectric layer, a gate, a source and a drain. The substrate includes a first region and a second region. The shallow trench isolation structure is arranged on the first region and the second region, and the shallow trench isolation structure is lower than a surface of the substrate and forms an opening. The dielectric layer is arranged in the opening and on the substrate, and a height of the dielectric layer in the second region is greater than that in the first region. The gate is arranged on the dielectric layer. The source is arranged on the substrate and located on a side of the gate. The drain is arranged on the substrate and located on the other side of the gate.
    Type: Application
    Filed: March 22, 2023
    Publication date: December 21, 2023
    Applicant: NEXCHIP SEMICONDUCTOR CORPORATION
    Inventors: CHIH-NAN WU, WEI PANG CHEN, CHI-CHERNG JENG
  • Publication number: 20230108974
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The photo sensitive regions are in the semiconductor substrate. The dielectric layer is over a backside surface of the semiconductor substrate. The grid structure is over a backside surface of the dielectric layer. The grid structure includes a plurality of grid lines. Each of the grid lines comprises a lower portion and an upper portion forming an interface with the lower portion. The convex dielectric lenses are alternately arranged with the grid lines over the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are higher than an interface between the upper portion and the lower portion of each of the grid lines.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 6, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Patent number: 11522001
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: December 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Publication number: 20220336348
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 11404368
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 11257953
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10998415
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20210043670
    Abstract: An image sensor device includes a semiconductor device, a plurality of photo sensitive regions, a dielectric layer, a grid structure, and a plurality of convex dielectric lenses. The plurality of photo sensitive regions are in the semiconductor substrate. The dielectric layer is on a backside surface of the semiconductor substrate facing away from the plurality of photo sensitive regions. The grid structure is on a backside surface of the dielectric layer facing away from the semiconductor substrate. The grid structure includes a plurality of grid lines spaced from each other. The plurality of convex dielectric lenses are alternately arranged with the plurality of grid lines of the grid structure on the backside surface of the dielectric layer. Apexes of the plurality of convex dielectric lenses are lower than top ends of the plurality of grid lines of the grid structure.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Publication number: 20200350244
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Patent number: 10818716
    Abstract: An image sensor device includes a substrate, a pixel circuit, a dielectric structure, a photo sensitive element, a grid, and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The pixel circuit is disposed on the first side of the substrate. The dielectric structure is disposed on the second side of the substrate. The photo sensitive element is disposed between the pixel circuit and the dielectric structure. The grid is disposed on the dielectric structure. The convex dielectric lens is disposed on the dielectric structure. The convex dielectric lens has a convex side. A topmost of the convex side is above an interface between the dielectric structure and the grid.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Patent number: 10797176
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10720386
    Abstract: An integrated circuit structure includes a dielectric layer and an etch stop layer. The etch stop layer includes a first sub layer including a metal nitride over the first dielectric layer, and a second sub layer overlying or underlying the first sub layer. The second sub layer includes a metal compound comprising an element selected from carbon and oxygen, and is in contact with the first sub layer.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Tsung-Hsuan Hong, Chun Che Lin, Chih-Nan Wu
  • Publication number: 20200098883
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 26, 2020
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20200066911
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku
  • Patent number: 10522640
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Publication number: 20190348458
    Abstract: An image sensor device includes a substrate, a pixel circuit, a dielectric structure, a photo sensitive element, a grid, and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The pixel circuit is disposed on the first side of the substrate. The dielectric structure is disposed on the second side of the substrate. The photo sensitive element is disposed between the pixel circuit and the dielectric structure. The grid is disposed on the dielectric structure. The convex dielectric lens is disposed on the dielectric structure. The convex dielectric lens has a convex side. A topmost of the convex side is above an interface between the dielectric structure and the grid.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko JANGJIAN, Chih-Nan WU, Chun-Che LIN, Yu-Ku LIN
  • Patent number: 10367021
    Abstract: An image sensor device includes a substrate, a photo sensitive element, a first dielectric structure and a convex dielectric lens. The substrate has a first side and a second side opposite to the first side. The photo sensitive element is formed on the first side of the substrate for receiving incident light transmitted through the substrate. The first dielectric structure is formed on the second side of the substrate. At least one portion of the convex dielectric lens is located in the first dielectric structure. The convex dielectric lens has a convex side oriented toward the incident light and a planar side oriented toward the photo sensitive element.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shiu-Ko Jangjian, Chih-Nan Wu, Chun-Che Lin, Yu-Ku Lin
  • Publication number: 20190058063
    Abstract: An improved conductive feature for a semiconductor device and a technique for forming the feature are provided. In an exemplary embodiment, the semiconductor device includes a substrate having a gate structure formed thereupon. The gate structure includes a gate dielectric layer disposed on the substrate, a growth control material disposed on a side surface of the gate structure, and a gate electrode fill material disposed on the growth control material. The gate electrode fill material is also disposed on a bottom surface of the gate structure that is free of the growth control material. In some such embodiments, the gate electrode fill material contacts a first surface and a second surface that are different in composition.
    Type: Application
    Filed: October 22, 2018
    Publication date: February 21, 2019
    Inventors: Chih-Nan Wu, Shiu-Ko JangJian, Chun Che Lin, Wen-Cheng Hsuku