Patents by Inventor Chih-Ning Wu

Chih-Ning Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6453915
    Abstract: A method of cleaning polycide gates after an etching step. A gate oxide layer, a polysilicon layer, a titanium nitride layer, a silicide layer, an anti-reflection layer and a patterned photoresist layer are sequentially formed over a substrate. An etching operation is next carried out to form a gate structure. The gate structure is formed by patterning the polysilicon layer, the titanium nitride layer and the silicide layer. The gate structure is subsequently cleaned in a three-step cleaning operation. In the first cleaning step, minute amount of fluoride-containing compound, hydrogen and inert gas are used as gaseous reactants in a plasma-cleaning operation. The fluoride-containing compound is capable of initiating a free radical chain reaction. In the second cleaning step, a solvent containing ammonium ions is applied to the gate structure. In the third cleaning step, a solution formed by dissolving oxidizing agent in de-ionized water is applied.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: September 24, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Publication number: 20020119672
    Abstract: A post-etching cleaning method for removing high molecular weight compounds formed after an etching operation. After a dual damascene opening is formed by etching a dielectric layer over a substrate, a two-stage wet cleaning operation is conducted. In the first wet cleaning, a cleaning solution is used to wash the substrate. The cleaning solution contains hydrogen peroxide and benzotriazole. In the second wet cleaning, inorganic acid solution is used.
    Type: Application
    Filed: February 28, 2001
    Publication date: August 29, 2002
    Inventors: Chih-Ning Wu, Sun-Chieh Chien
  • Patent number: 6440873
    Abstract: A post metal etch cleaning method which begins by providing a wafer with an etched metal layer formed thereon, wherein the etched metal layer is covered with a polymer residue. A fluorine based organic acid solvent is used to clean the metal layer, followed by removing the solvent by a physical method. Next, a de-ionized water is applied to flush the metal layer before performing a drying step on the wafer to dry the metal layer.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: August 27, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Publication number: 20020113037
    Abstract: A method for removing fluorine-contained etching residues during dual damascene process comprises providing a dual damascene structure having a copper conductor structure therein, a cap layer formed on the copper conductor structure and the dual damascene structure, and a low dielectric constant dielectric layer on the cap layer. The low dielectric constant dielectric layer formed by spin-on polymer method has at least an opening above the copper conductor structure. The cap layer is etched by fluorine-contained plasma to expose the copper conductor structure. The dual damascene structure is cleaned with a solvent and then the fluorine-contained etching residues are removed by plasma sputtering treatment or baking, or combination of both. The addition of baking and plasma sputtering treatment can prevent poor adhesion between coming metal diffusion barrier layer and the low dielectric constant dielectric layer.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Inventors: Chih-Ning Wu, Cheng-Yuan Tsai, Chan-Lon Yang
  • Publication number: 20020115296
    Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and cap layer are then etched to expose partial the conductor structure. The etching residues are removed with an amine-contained solution and the amine-contained solution is removed with an intermediate solvent to avoid erosion of exposed the conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can prevent the conductor structure from erosion.
    Type: Application
    Filed: February 21, 2001
    Publication date: August 22, 2002
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Publication number: 20020115284
    Abstract: A method of cleaning a dual damascene structure includes forming a first conductive layer in a substrate. A dielectric layer is formed over the substrate. A dual damascene opening is formed in the dielectric layer to expose the first conductive layer. A H2O2 based aqueous solution is used to remove polymer residues in the dual damascene opening. A temperature of the H2O2 based aqueous solution is controlled so that the first conductive layer is not corroded. A diluted HF solution or a diluted HF and HCl solution is used to remove the polymer residues. A second conductive layer is formed over the substrate to fill the dual damascene opening. A chemical mechanical polishing process is performed with the dielectric layer serving as a polishing stop to remove the second conductive layer outside the dual damascene opening. A H2O2 based aqueous solution is used to clean the hydrocarbon particulates from the chemical mechanically polishing step.
    Type: Application
    Filed: February 20, 2001
    Publication date: August 22, 2002
    Applicant: United Microelectronics Corp., No. 3
    Inventors: Chih-Ning Wu, Chan-Lon Yang, Sun-Chieh Chien
  • Publication number: 20020111033
    Abstract: A post metal etch cleaning method which begins by providing a wafer with an etched metal layer formed thereon, wherein the etched metal layer is covered with a polymer residue. A fluorine based organic acid solvent is used to clean the metal layer, followed by removing the solvent by a physical method. Next, a de-ionized water is applied to flush the metal layer before performing a drying step on the wafer to dry the metal layer.
    Type: Application
    Filed: February 26, 2001
    Publication date: August 15, 2002
    Applicant: United Microelectronice Corp.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Patent number: 6303482
    Abstract: A method for cleaning the surface of a semiconductor wafer is disclosed. A plasma ashing process is performed on the surface of the semiconductor wafer. The plasma ashing process is performed in a chamber that contains oxygen and carbon tetrafluoride (CF4). An ozone-containing deionized (DI) water cleaning procedure, an amine-based solvent cleaning procedure and a fluoride-based solvent cleaning procedure are then performed to clean the surface of the semiconductor wafer without over-etching the silicon oxide of the street. Finally, an oxygen plasma cleaning process is performed to remove any residual photo-resist.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: October 16, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Patent number: 6060415
    Abstract: The present invention provides a molecular sieve composite membrane, which includes an anodic alumina membrane as a support and the uni-directionally oriented molecular sieve membrane grown in situ on the anodic alumina membrane. The close packing transitional metal containing aluminophosphate AFI molecular sieve crystals have successfully been grown on the anodic alumina. The molecular sieve phase bounded strongly and anchored into the anodic alumina membrane. Besides, the specific cylindrical channels of the anodic alumina membrane provides the template function to orient the growth of molecular sieves.
    Type: Grant
    Filed: February 10, 1997
    Date of Patent: May 9, 2000
    Assignee: National Science Council
    Inventors: Kuei-Jung Chao, Chih-Ning Wu, Han-Chang Shih, Tzeng-Guang Tsai