Patents by Inventor Chih-Shan Chen
Chih-Shan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10937894Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.Type: GrantFiled: January 13, 2020Date of Patent: March 2, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 10868005Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: GrantFiled: December 19, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Wen Cheng, Chih-Shan Chen, Wei-Yang Lo
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Patent number: 10763366Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: GrantFiled: October 16, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Publication number: 20200273993Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: ApplicationFiled: May 11, 2020Publication date: August 27, 2020Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Publication number: 20200152775Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.Type: ApplicationFiled: January 13, 2020Publication date: May 14, 2020Inventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 10651309Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: GrantFiled: July 30, 2018Date of Patent: May 12, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Patent number: 10636788Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.Type: GrantFiled: July 31, 2018Date of Patent: April 28, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
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Publication number: 20200126983Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Inventors: Tung-Wen Cheng, Chih-Shan Chen, Wei-Yang Lo
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Publication number: 20200119161Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.Type: ApplicationFiled: December 16, 2019Publication date: April 16, 2020Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Chih Hsuan Cheng, Tzu-Chan Weng
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Publication number: 20200075590Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
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Publication number: 20200052121Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Patent number: 10535757Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.Type: GrantFiled: December 17, 2018Date of Patent: January 14, 2020Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 10522408Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.Type: GrantFiled: December 21, 2018Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
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Patent number: 10515958Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: GrantFiled: July 31, 2018Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Wen Cheng, Chih-Shan Chen, Wei-Yang Lo
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Patent number: 10510875Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.Type: GrantFiled: June 5, 2018Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Chih Hsuan Cheng, Tzu-Chan Weng
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Patent number: 10497701Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.Type: GrantFiled: March 28, 2016Date of Patent: December 3, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
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Publication number: 20190198646Abstract: A fin field effect transistor (FinFET) includes a fin extending from a substrate, where the fin includes a lower region, a mid region, and an upper region, the upper region having sidewalls that extend laterally beyond sidewalls of the mid region. The FinFET also includes a gate stack disposed over a channel region of the fin, the gate stack including a gate dielectric, a gate electrode, and a gate spacer on either side of the gate stack. A dielectric material is included that surrounds the lower region and the first interface. A fin spacer is included which is disposed on the sidewalls of the mid region, the fin spacer tapering from a top surface of the dielectric material to the second interface, where the fin spacer is a distinct layer from the gate spacers. The upper region may include epitaxial source/drain material.Type: ApplicationFiled: December 17, 2018Publication date: June 27, 2019Inventors: Wei-Yang Lee, Chih-Shan Chen
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Publication number: 20190131176Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.Type: ApplicationFiled: December 21, 2018Publication date: May 2, 2019Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
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Publication number: 20190035908Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.Type: ApplicationFiled: June 5, 2018Publication date: January 31, 2019Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Chih Hsuan Cheng, Tzu-Chan Weng
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Patent number: 10163715Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.Type: GrantFiled: October 20, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng