Patents by Inventor Chih-Shan Chen
Chih-Shan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10163898Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: GrantFiled: July 1, 2016Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Wen Cheng, Wei-Yang Lo, Chih-Shan Chen
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Patent number: 10158006Abstract: An exemplary method for forming a semiconductor device includes etching a top portion etching a top portion of a first semiconductor fin to produce a recessed top portion of the fin. A dielectric layer is deposited over the first semiconductor fin and an adjacent isolation structure. The top surface of the recessed top portion is exposed where a resulting pair of spacers remains on either side of the recessed top portion, the spacers being in contact with sidewalls of the recessed fin. The fin is further recessed to produce a recessed top surface of the first semiconductor fin, the recessed top surface being below a top surface of the isolation structure. A source/drain material is epitaxially grown in the recess between the pair of spacers and expands laterally over the pair of spacers.Type: GrantFiled: December 28, 2016Date of Patent: December 18, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yang Lee, Chih-Shan Chen
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Publication number: 20180350809Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: ApplicationFiled: July 31, 2018Publication date: December 6, 2018Inventors: Tung-Wen Cheng, Chih-Shan Chen, Wei-Yang Lo
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Publication number: 20180337180Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.Type: ApplicationFiled: July 31, 2018Publication date: November 22, 2018Inventors: Tung-Wen Cheng, Chih-Shan Chen, Mu-Tsang Lin
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Publication number: 20180337283Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: ApplicationFiled: July 30, 2018Publication date: November 22, 2018Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Patent number: 10038095Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: GrantFiled: August 12, 2016Date of Patent: July 31, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Publication number: 20180151440Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.Type: ApplicationFiled: October 20, 2017Publication date: May 31, 2018Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
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Patent number: 9812363Abstract: A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess.Type: GrantFiled: February 17, 2017Date of Patent: November 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Ying Ting Hsia, Tzu-Chan Weng
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Publication number: 20170309624Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.Type: ApplicationFiled: July 1, 2016Publication date: October 26, 2017Inventors: Tung-Wen Cheng, Wei-Yang Lo, Chih-Shan Chen
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Publication number: 20170222053Abstract: A semiconductor device includes a semiconductor base. A dielectric isolation structure is formed in the semiconductor base. A source/drain of a FinFET transistor is formed on the semiconductor base. A bottom segment of the source/drain is embedded into the semiconductor base. The bottom segment of the source/drain has a V-shaped cross-sectional profile. The bottom segment of the source/drain is separated from the dielectric isolation structure by portions of the semiconductor base.Type: ApplicationFiled: August 12, 2016Publication date: August 3, 2017Inventors: Chii-Horng Li, Chih-Shan Chen, Roger Tai, Yih-Ann Lin, Yen-Ru Lee, Tzu-Ching Lin
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Publication number: 20170179120Abstract: A semiconductor device includes a semiconductor substrate, a plurality of semiconductor fins, a gate stack and an epitaxy structure. The semiconductor fins are present on the semiconductor substrate. The semiconductor fins respectively include recesses therein. The gate stack is present on portions of the semiconductor fins that are adjacent to the recesses. The epitaxy structure is present across the recesses of the semiconductor fins. The epitaxy structure includes a plurality of corners and at least one groove present between the corners, and the groove has a curvature radius greater than that of at least one of the corners.Type: ApplicationFiled: March 28, 2016Publication date: June 22, 2017Inventors: Tung-Wen CHENG, Chih-Shan CHEN, Mu-Tsang LIN
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Publication number: 20170110558Abstract: An exemplary method for forming a semiconductor device includes etching a top portion etching a top portion of a first semiconductor fin to produce a recessed top portion of the fin. A dielectric layer is deposited over the first semiconductor fin and an adjacent isolation structure. The top surface of the recessed top portion is exposed where a resulting pair of spacers remains on either side of the recessed top portion, the spacers being in contact with sidewalls of the recessed fin. The fin is further recessed to produce a recessed top surface of the first semiconductor fin, the recessed top surface being below a top surface of the isolation structure. A source/drain material is epitaxially grown in the recess between the pair of spacers and expands laterally over the pair of spacers.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Inventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 9537008Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.Type: GrantFiled: August 17, 2015Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 9527721Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package with an anti-stiction layer, and an associated method of formation. In some embodiments, the MEMS package comprises a device substrate and a CMOS substrate. The device substrate comprises a MEMS device having a moveable or flexible part that is movable or flexible with respect to the device substrate. A surface of the moveable or flexible part is coated by a conformal anti-stiction layer made of polycrystalline silicon. A method for manufacturing the MEMS package is also provided.Type: GrantFiled: May 15, 2015Date of Patent: December 27, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shyh-Wei Cheng, Chao-Po Lu, Chung-Hsien Hun, Chih-Shan Chen, Chuan-Yi Ko, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
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Publication number: 20160332863Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package with an anti-stiction layer, and an associated method of formation. In some embodiments, the MEMS package comprises a device substrate and a CMOS substrate. The device substrate comprises a MEMS device having a moveable or flexible part that is movable or flexible with respect to the device substrate. A surface of the moveable or flexible part is coated by a conformal anti-stiction layer made of polycrystalline silicon. A method for manufacturing the MEMS package is also provided.Type: ApplicationFiled: May 15, 2015Publication date: November 17, 2016Inventors: Shyh-Wei Cheng, Chao-Po Lu, Chung-Hsien Hun, Chih-Shan Chen, Chuan-Yi Ko, Chih-Yu Wang, Hsi-Cheng Hsu, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu
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Publication number: 20150357469Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises an isolation structure comprising a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; a strained material in the cavity and extending above the top surface, wherein the strained material comprises an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.Type: ApplicationFiled: August 17, 2015Publication date: December 10, 2015Inventors: Wei-Yang Lee, Chih-Shan Chen
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Patent number: 9112033Abstract: The disclosure relates to a semiconductor device having an isolation structure with a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; and a strained material in the cavity and extending above the top surface. The strained material has an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.Type: GrantFiled: December 30, 2013Date of Patent: August 18, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yang Lee, Chih-Shan Chen
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Publication number: 20150187943Abstract: The disclosure relates to a semiconductor device having an isolation structure with a top surface over a substrate major surface; a cavity having a convex bottom surface below the top surface; and a strained material in the cavity and extending above the top surface. The strained material has an upper portion having a rhombus shape and a lower portion having substantially vertical sidewalls; and a pair of tapered spacers adjoining a portion of the substantially vertical sidewalls above the top surface.Type: ApplicationFiled: December 30, 2013Publication date: July 2, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Yang Lee, Chih-Shan Chen