Abstract: A manufacturing method of a package structure includes: forming a first package component, where the first package component includes a first insulating encapsulation laterally covering semiconductor dies and a redistribution structure formed on the first insulating encapsulation and the semiconductor dies; coupling the first package component to a second package component; forming an underfill layer between the first and second package component, where the underfill layer extends to cover a sidewall of the first package component; forming a metallic layer on opposing surfaces of the semiconductor dies and the first insulating encapsulation by using a jig, where a window of the jig accessibly exposes the opposing surfaces of the semiconductor dies and the first insulating encapsulation, and a peripheral region of the opposing surface of the first insulating encapsulation is shielded by the jig.

Abstract: A method for forming transistors includes forming a stack of alternating first semiconductor layers and second semiconductor layers on a substrate and forming nanostructure channels and interposers by forming a source/drain opening in a first device region of the substrate. The source/drain opening extending through the first and second semiconductor layers. The method includes, after the forming a source/drain opening, increasing tensile strain of the nanostructure channels, and, after the increasing tensile strain, forming a source/drain in the source/drain opening.

Abstract: A medical image analysis system comprises: a database for storing a first medical image data indicating a target medical image; and a server for accessing the database. The server includes: a first analysis module for generating a first determination data according to the first medical image data; a second analysis module for generating a second determination data according to the first medical image data; and an ensemble module communicatively connected with the first and second analysis modules and generating a third determination data according to the first and second determination data. The first and second determination data each indicate whether the target medical image includes a cancerous tissue image or indicate a chance of the target medical image including a cancerous tissue image. The third determination data indicates whether the target medical image includes a cancerous tissue image.

Abstract: The present application provides a method for predicting energy consumption and an electronic device. The electronic device obtains energy efficiency data of a target device within a preset time period, and determines a plurality of influencing factors from the energy efficiency data according to a preset energy efficiency indicator and a feature extraction algorithm. The electronic device further determines a regression prediction model according to the plurality of influencing factors and the preset energy efficiency indicator, inputs the plurality of influencing factors into the regression prediction model and generates a first prediction value at each moment within the preset time period, and generates a trend graph of energy consumption corresponding to the preset time period according to a first predicted value at each moment. The present application is able to improve an efficiency of predicting energy consumption.

Abstract: A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first input terminal is configured to receive the first power source. The first output terminal is electrically connected to a ground terminal. The first switch circuit is electrically connected to the first input terminal and the ground terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be turned on, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be turned off.

Abstract: A self-protection circuitry is configured to receive a first power source. The self-protection circuitry includes a first transistor circuit, a first switch circuit, and a control circuit. The first transistor circuit includes a first input terminal, a first output terminal, and a first control terminal. The first output terminal is electrically connected to a ground terminal, and the first input terminal is configured to receive the first power source. The first switch circuit is electrically connected to the first control terminal and the first input terminal. The control circuit is electrically connected to the first switch circuit, and is configured to: before the first power source supplies power to the first transistor circuit, control the first switch circuit to be 10 conducted, and after the first power source continuously supplies power to the first transistor circuit, control the first switch circuit to be cut off.

Abstract: A method includes treating a burled surface of an object using radiation or heat and setting parameters of the radiation or heat to effectuate a predetermined surface strength, hardness, roughness, coefficient of friction, chemical resistance, wear resistance, and/or corrosion of the burled surface.

Abstract: The present disclosure provides a method and a system therefore for processing wafer. The method includes: extracting a first gas from a chamber via a first route; blocking a second route used to be pumped down to chuck a wafer placed in the chamber, wherein the second route connects the chamber and the first route; and providing a second gas via a third route to purge a junction of the first route and the second route.

Abstract: A radio frequency apparatus includes a power amplifier circuit, a signal coupling circuit, an extraction circuit, and a harmonic filter circuit. The power amplifier circuit is configured to amplify a differential signal to output a to-be-filtered signal. The signal coupling circuit includes a primary side inductor and a secondary side inductor. The signal coupling circuit is configured to convert the to-be-filtered signal received by the primary side inductor into a single-ended signal outputted from the secondary side inductor. The extraction circuit has a center tap. The extraction circuit is configured to inductively couple to the primary side inductor and output a common mode signal from the center tap. The harmonic filter circuit is configured to perform a harmonic filtering on the single-ended signal according to the common mode signal, such that the secondary side inductor of the signal coupling circuit outputs a filtered signal.

Abstract: Some embodiments relate to a method that includes depositing a first layer of hard mask material over a layer of dielectric material; etching the first layer of the hard mask material, the etched first layer of hard mask material including an etched portion having a first lateral dimension; depositing a second layer of the hard mask material over the first layer of the hard mask material; etching at least a portion of the second layer of the hard mask material, while allowing a remaining portion of the hard mask material, to expose a portion of the layer of the dielectric material that has a second lateral dimension less than the first lateral dimension; and etching a trench into the layer of the dielectric material at the exposed portion of the layer of the dielectric material.

Abstract: An electronic device may have a display with pixels configured to display an image. The pixels may be overlapped by a cover layer. The display may have peripheral edges with curved cross-sectional profiles. An inactive area in the display may be formed along a peripheral edge of the display or may be surrounded by the pixels. Electrical components such as optical components may be located in the inactive area. An image transport layer may be formed from a coherent fiber bundle or Anderson localization material. The image transport layer may overlap the pixels, may have an opening that overlaps portions of the inactive area, may have an output surface that overlap portions of the inactive area, and/or may convey light associated with optical components in the electronic device.

Abstract: In some embodiments, the present disclosure relates to a method of forming a transistor device. The method includes forming a source contact over a substrate, forming a drain contact over the substrate, and forming a gate contact material over the substrate. The gate contact material is patterned to define a gate structure that wraps around the source contact along a continuous and unbroken path.

Abstract: An augmented logarithmic spiral antenna structure includes a first conductive layer, a dielectric layer and a second conductive layer. The first conductive layer includes a first spiral arm and a plurality of second spiral arms. The first spiral arm includes a first initial radius. The second spiral arms are disposed around and connected to the first spiral arm, and each of the second spiral arms includes a second initial radius. The dielectric layer has a top surface and a bottom surface, and the top surface is connected to the first conductive layer. The second conductive layer is connected to the bottom surface. A plurality of the second initial radii of the second spiral arms are different from each other, and different from the first initial radius.

Abstract: Embodiments of this disclosure provide a semiconductor structure including a substrate. The substrate includes active areas and insulation areas between the active areas. A first end of each of the active areas has a first head portion, a second end of each of the active areas has the second head portion, and a middle portion of each of active areas has a waist portion. In a top view, the first head portion and the second head portion of each of the active areas have a first width, respectively, and the waist portion of each of the active areas has a second width. Also, the first width is greater than the second width. Moreover, a method of manufacturing a semiconductor structure also is provided herein.

Abstract: A portable computer having flexible display including a housing, a motor, a transmission gear set, a linkage set, and a flexible display is provided. The housing includes a fixing portion and a moving portion movably connected to and partially overlapped on the fixing portion. The motor, the transmission gear set, and the linkage set are disposed in the housing respectively. The linkage set and the transmission gear set are coupled to each other to be a connection and drive mechanism of the fixing portion and the moving portion. A portion of the flexible display is assembled to the fixing portion, and an end portion of the flexible display passes by the moving portion and are wound and stored at a backside of the portion of the flexible display.

Abstract: A semiconductor device structure includes nanostructures formed over a substrate. The structure also includes a fin isolation structure formed beside the nanostructures. The structure also includes a work function layer surrounding the nanostructures and covering a sidewall of the fin isolation structure. The structure also includes a gate electrode layer covering the work function layer. The gate electrode layer has an extending portion surrounded by the work function layer.

Abstract: A method of making a semiconductor device includes manufacturing an ESD cell over a substrate, wherein the ESD cell includes multiple diodes connected in parallel to each other. The method includes manufacturing a conductive pillar electrically connected to the ESD cell of the semiconductor device; manufacturing a through-silicon via (TSV) extending through the substrate, wherein the TSV extends through the substrate within a TSV zone having a TSV zone perimeter, and wherein a first end of the TSV is at a same side of the substrate as the ESD cell, and a second end of the TSV is at a different side of the substrate from the ESD cell. The method includes manufacturing an antenna extending parallel to the TSV at a same side of the substrate as the ESD cell; and manufacturing an antenna pad electrically connected to the TSV, the antenna, and the conductive pillar.

Abstract: A semiconductor structure includes a first semiconductor package, a second semiconductor package, a heat spreader and an dielectric layer. The first semiconductor package includes a plurality of first semiconductor chips and a first dielectric encapsulation layer disposed around the plurality of the first semiconductor chips. The second semiconductor package is disposed over and corresponds to one of the plurality of first semiconductor chips, wherein the second semiconductor package includes a plurality of second semiconductor chips and a second dielectric encapsulation layer disposed around the plurality of second semiconductor chips. The heat spreader is disposed over and corresponds to another of the plurality of first semiconductor chips. The dielectric layer is disposed over the first semiconductor package and around the second semiconductor package and the heat spreader.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a first liner is deposited to line a recess between a first semiconductor fin and a second semiconductor fin, the first liner comprising a first material. The first liner is annealed to transform the first material to a second material. A second liner is deposited to line the recess, the second liner comprising a third material. The second liner is annealed to transform the third material to a fourth material.

Abstract: A package structure including an organic interposer substrate, a semiconductor die, conductive bumps, an underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die.