Abstract: A chemical mechanical polishing apparatus includes a platen to hold a polishing pad, a carrier to hold a substrate against a polishing surface of the polishing pad during a polishing process, a polishing liquid dispenser having a polishing liquid port positioned over the platen to deliver polishing liquid onto the polishing pad, a temperature control system including coolant liquid fluid reservoirs for containing coolant fluids, a thermal controller configured to control the temperature of the coolant fluid within the coolant fluid reservoirs, and a first dispenser having openings in fluid connection with the coolant fluid reservoirs, the openings positioned configured to spray an aerosolized coolant liquid directly onto the polishing pad, and a second dispenser having a coolant port in fluid connection with the coolant fluid reservoirs, the coolant port positioned over the platen and configured to flow a stream of coolant liquid directly onto the polishing pad.

Abstract: A system may include a gimbal defining a plurality of pockets, where each pocket may include a first portion and a second portion that extends between the first portion and a base of the pocket. The second portion may have a greater diameter than the first portion. The system may include a plurality of conditioning disks, where each conditioning disk is seated within the first portion of a respective pocket. The system may include a plurality of gaskets, where each gasket is seated within the second portion of a respective pocket. The system may include a plurality o-rings, each o-ring disposed between a peripheral edge of one of the plurality of conditioning disks and a lateral wall of one of the plurality of pockets. The system may include a plurality of shoulder screws for coupling the gimbal with one of the plurality of gaskets and a conditioning disk.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A heat dissipation device includes a vapor chamber for contacting a heat source; at least one heat pipe having a first end and a second end connected to the vapor chamber; at least one partition disposed inside the heat pipe to partition the inside of the heat pipe into a first channel and a second channel isolated from each other; and a heat dissipation fin set disposed on the vapor chamber and partially covers the heat pipe. The vapor chamber is filled with a liquid working medium that absorbs the heat of the heat source and then gasifies into a gaseous working medium. The gaseous working medium moves into the first channel and the second channel to be condensed by the heat dissipation fin set, so the gaseous working medium is liquefied into the liquid working medium, and then the liquid working medium flows back into the vapor chamber.

Abstract: A multiple detection system is applied to a vehicle and includes a contact-type detection module adapted to generate a contact-type detection datum, a contactless-type detection module adapted to generate a contactless-type detection datum, and an operation processor electrically connected with the contact-type detection module and the contactless-type detection module in a wire manner or in a wireless manner. The operation processor sets at least one of the contact-type detection datum and the contactless-type detection datum according to an environmental status of the vehicle to be a main detection result of the multiple detection system, and further sets the other detection datum to be an auxiliary detection result of the multiple detection system, for acquiring a passenger feature inside the vehicle.

Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A method of making a semiconductor device includes manufacturing a first transistor over a first side of a substrate. The method further includes depositing a spacer material against a sidewall of the first transistor. The method further includes recessing the spacer material to expose a first portion of the sidewall of the first transistor. The method further includes manufacturing a first electrical connection to the transistor, a first portion of the electrical connection contacts a surface of the first transistor farthest from the substrate, and a second portion of the electrical connect contacts the first portion of the sidewall of the first transistor. The method further includes manufacturing a self-aligned interconnect structure (SIS) extending along the spacer material, wherein the spacer material separates a portion of the SIS from the first transistor, and the first electrical connection directly contacts the SIS.

Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.

Abstract: An antenna assembly includes a patch antenna, a metal layer, and a feed-in signal layer. The metal layer is disposed on a side of the patch antenna and includes a first slot and a second slot. The feed-in signal layer is disposed on a side of the metal layer opposite the second antenna and includes a transmitting port, a receiving port, a hybrid coupler, and two microstrips. The transmitting port and the receiving port are connected to the hybrid coupler, and the two microstrips are extended in the direction away from the hybrid coupler. Projections of two ends of the two microstrips onto the metal layer are overlapped with the first slot and the second slot. An antenna array is also mentioned.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Abstract: A digital compute-in-memory (DCIM) system includes a first DCIM macro. The first DCIM macro includes a first memory cell array and a first arithmetic logic unit (ALU). The first memory cell array has N rows that are configured to store weight data of a neural network in a single weight data download session, wherein N is a positive integer not smaller than two. The first ALU is configured to receive a first activation input, and perform convolution operations upon the first activation input and a single row of weight data selected from the N rows of the first memory cell array to generate first convolution outputs.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

Abstract: A digital compute-in-memory (DCIM) macro includes a memory cell array and an arithmetic logic unit (ALU). The memory cell array stores weight data of a neural network. The ALU receives parallel bits of a same input channel in an activation input, and generates a convolution computation output of the parallel bits and target weight data in the memory cell array.

Abstract: A beam management method of an electronic device includes transmitting a detecting signal, receiving a reflecting signal of the detecting signal, determining blocked antennas of an antenna array of the electronic device according to the reflecting signal, and exciting only unblocked antennas of the antenna array. This will improve the radiation efficiency of the antenna array.

Abstract: The present invention provides a method for preparing an activated carbon, which includes impregnating a carbonaceous material with carbonated water; and exposing the carbonaceous material to microwave radiation to produce the activated carbon.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The substrate has a base and a multilayer structure over the base, and the gate stack wraps around the multilayer structure. The method includes partially removing the multilayer structure, which is not covered by the gate stack. The multilayer structure remaining under the gate stack forms a multilayer stack, and the multilayer stack includes a sacrificial layer and a channel layer over the sacrificial layer. The method includes partially removing the sacrificial layer to form a recess in the multilayer stack. The method includes forming an inner spacer layer in the recess and a bottom spacer over a sidewall of the channel layer. The method includes forming a source/drain structure over the bottom spacer. The bottom spacer separates the source/drain structure from the channel layer.

Abstract: The present invention relates to compounds with high chemical stability and methods for inhibiting the pathological activity of NETs in a subject. In particular, the invention relates to compounds with high chemical stability, uses thereof and methods for inhibiting or ameliorating NET mediated ailments (such as, for example, sepsis, systemic immune response syndrome (SIRS) and ischemia reperfusion injury (IRI)). More particularly, the invention relates to methods and uses of a polyanionic sulfated cellobioside modified with a small uncharged glycosidically linked substituent at its reducing terminus, wherein the presence of the substituent results in a molecule with high chemical stability without affecting the ability of the molecule to be effective in the therapy of NET mediated ailments. For example, the present invention relates to methods and uses of ?-O-methyl cellobioside sulfate (mCBS) or a pharmaceutically acceptable salt thereof (e.g., mCBS.