Patents by Inventor Chih-Wei Chang

Chih-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817452
    Abstract: A bus system is provided. The bus system includes a master device, an enhanced serial peripheral interface (eSPI) bus, a plurality of slave devices electrically connected to the master device via the eSPI bus, and a first resistor. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert handshake control line. The first resistor is coupled between the alert handshake control line and a power supply. Each slave device obtains the number of slave devices according to a first voltage of the alert handshake control line.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 27, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Chun-Wei Chiu, Hao-Yang Chang
  • Publication number: 20200335597
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Min-Hsiu HUNG, Yi-Hsiang CHAO, Kuan-Yu YEH, Kan-Ju LIN, Chun-Wen NIEH, Huang-Yi HUANG, Chih-Wei CHANG, Ching-Hwanq SU
  • Publication number: 20200335694
    Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a dielectric protection layer having sidewalls defining an opening over a conductive interconnect within an inter-level dielectric (ILD) layer. A bottom electrode structure extends from within the opening to directly over the dielectric protection layer. A variable resistance layer is over the bottom electrode structure and a top electrode is over the variable resistance layer. A top electrode via is disposed on the top electrode and directly over the dielectric protection layer.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 22, 2020
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • Patent number: 10809794
    Abstract: An example method is provided in according with one implementation of the present disclosure. The method includes identifying an intention of a user of a system in relation to a three-dimensional (3D) virtual object and selecting a 3D navigation mode from a plurality of 3D navigation modes based on the identified user intention. The plurality of 3D navigation modes includes at least a model navigation mode, a simple navigation mode, a driving navigation mode, a reaching navigation mode, and a multi-touch navigation mode. The method further includes transitioning the system to the selected 3D navigation mode.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: October 20, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chih Pin Hsiao, Gregory William Cook, Jishang Wei, Mithra Vankipuram, Nelson L Chang
  • Publication number: 20200328154
    Abstract: Disclosed herein is a method of forming a semiconductor structure. The method includes the steps of: forming a first dielectric layer having a first through hole on a precursor substrate, in which the first through hole passes through the first dielectric layer; filling a sacrificial material in the first through hole; forming a second dielectric layer having a second through hole over the first dielectric layer, in which the second through hole exposes the sacrificial material in the first through hole, and the second through hole has a bottom width less than a top width of the first through hole; removing the sacrificial material after forming the second dielectric layer having the second through hole; forming a barrier layer lining sidewalls of the first and second through holes; and forming a conductive material in the first and second through holes.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 15, 2020
    Inventors: Yu-Wei JIANG, Kuo-Pin CHANG, Chih-Wei HU
  • Publication number: 20200326134
    Abstract: A flexible vapor chamber for an electronic device includes an upper cover, a lower cover, an accommodation space, a capillary structure, plural support structures and a working fluid. The upper cover is made of a first flexible material. The lower cover is made of a second flexible material. The accommodation space is arranged between the upper cover and the lower cover. The capillary structure is disposed on the lower cover and accommodated within the accommodation space. The plural support structures are disposed on the upper cover and accommodated within the accommodation space. The plural support structures are contacted with the capillary structure. The working fluid is accommodated within the accommodation space. The flexible vapor chamber is permitted to be subjected to a flexural action in a flexible range. Consequently, the installation of the flexible vapor chamber complies with a shape of the electronic device.
    Type: Application
    Filed: March 18, 2020
    Publication date: October 15, 2020
    Inventors: CHIH-WEI CHEN, CHE-WEI KUO, TIEN-YAO CHANG, HSIANG-CHIH CHUANG
  • Patent number: 10804365
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: October 13, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
  • Patent number: 10796759
    Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Chieh Yang, Chih-Yang Chang, Chang-Sheng Liao, Hsia-Wei Chen, Jen-Sheng Yang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Manish Kumar Singh, Chi-Tsai Chen
  • Patent number: 10787408
    Abstract: A method for producing 9,9-bis(3-phenyl-4-(2-hydroxyethoxy)phenyl)fluorene is provided. The method includes the steps of: performing a condensation reaction with fluorenone and 2-[(2-phenyl)phenoxy]ethanol in the presence of a catalyst and co-catalyst, wherein the catalyst is alkylsulfonic acid, and the co-catalyst is a mercapto-containing compound, thereby effectively reducing the formation of a by-product, such that the product has characteristics of low chroma, high purity, and high yield.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: September 29, 2020
    Assignee: CHINA PETROCHEMICAL DEVELOPMENT CORPORATION
    Inventors: Ding-Chi Huang, Yu-Sen Chen, Chih-Wei Chang, Wei-Ying Li
  • Patent number: 10775237
    Abstract: Disclosed is a resonant wavelength measurement apparatus, including a light source and a measurement unit. The measurement unit has a guided-mode resonance filter and a photosensitive element. The guided-mode resonance filter has a plurality of resonant areas, and each resonant area has a different filtering characteristic, to receive first light in the light source transmitted by a sensor or receive second light in the light source reflected by the sensor. The first light has a first corresponding pixel on the photosensitive element, the second light has a second corresponding pixel on the photosensitive element, and the first corresponding pixel and the second corresponding pixel correspond to a same resonant wavelength.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: September 15, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Cheng-Sheng Huang, Chih-Wei Chang, Shi-Ting Chen
  • Patent number: 10777423
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tung-Kai Chen, Ching-Hsiang Tsai, Kao-Feng Liao, Chih-Chieh Chang, Chun-Hao Kung, Fang-I Chih, Hsin-Ying Ho, Chia-Jung Hsu, Hui-Chi Huang, Kei-Wei Chen
  • Patent number: 10773074
    Abstract: In certain embodiments an electrode array for epidural stimulation of the spinal cord is provided where the array comprises a plurality of electrodes disposed on a flexible polymer substrate; said electrodes being electrically connected to one or more lead wires and/or connection points on an electrical connector; where the electrodes of said array are bonded to said polymer so that the electrodes can carry an electrical stimulation signal having a voltage, frequency, and current sufficient to provide epidural stimulation of a spinal cord and/or brain in vivo or in a physiological saline solution, without separation of all or a part of an electrode from the polymer substrate.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: September 15, 2020
    Assignee: The Regents of the University of California
    Inventors: Wentai Liu, Victor Reggie Edgerton, Chih-Wei Chang, Parag Gad
  • Publication number: 20200279743
    Abstract: A method for semiconductor manufacturing includes providing a substrate, forming a patterning layer over the substrate, and patterning the patterning layer to form a hole in the patterning layer. The method also includes applying a first directional etching to two inner sidewalls of the hole to expand the hole along a first direction and applying a second directional etching to another two inner sidewalls of the hole to expand the hole along a second direction that is different from the first direction.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Patent number: 10761359
    Abstract: A touch display device including a first substrate, a second substrate, a display medium, and a pixel array structure is provided. The pixel array structure includes a scan line, a data line, an active device, pixel electrodes, a signal electrode layer and a signal transmission layer. The scan line intersects the data line. The active device is connected to the scan line and the data line. The pixel electrodes are arranged in an array. The signal electrode layer includes signal electrodes. The signal transmission layer includes a signal line disposed between two adjacent columns of the pixel electrodes and electrically connected to one of the signal electrodes. The data line includes at least a portion located outside of the signal line.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 1, 2020
    Assignee: Innolux Corporation
    Inventors: Hung-Kun Chen, Hsieh-Li Chou, Li-Wei Sung, Tung-Kai Liu, Chia-Hao Tsai, Chih-Hao Chang, Bo-Feng Chen, Yu-Chien Kao
  • Patent number: 10763365
    Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Liang Chen, Chih-Ming Lai, Ching-Wei Tsai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kuo-Cheng Ching, Ru-Gun Liu, Wei-Hao Wu, Yi-Hsiung Lin, Chia-Hao Chang, Lei-Chun Chou
  • Patent number: 10763426
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20200271887
    Abstract: A lens structure includes a lens cone, at least one lens and an acrylate adhesive. The lens cone includes at least one contacting structure. The lens is disposed within the lens cone and abuts against the contacting structure. The acrylate adhesive covers an interface between the lens cone and the lens, wherein a coverage area of the acrylate adhesive accounts for more than 70% of a surface area of a side surface of the lens.
    Type: Application
    Filed: May 12, 2020
    Publication date: August 27, 2020
    Applicant: Rays Optics Inc.
    Inventors: Chen-Cheng Lee, Yu-Hua Huang, Chih-Wei Chang, Tzu-Lun Wang
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10749108
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: August 18, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20200258746
    Abstract: A method includes forming a source/drain region, and in a vacuum chamber or a vacuum cluster system, preforming a selective deposition to form a metal silicide layer on the source/drain region, and a metal layer on dielectric regions adjacent to the source/drain region. The method further includes selectively etching the metal layer in the vacuum chamber, and selectively forming a metal nitride layer on the metal silicide layer. The selectively forming the metal nitride layer is performed in the vacuum chamber or a vacuum cluster system without vacuum break.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Sung-Li Wang, Jyh-Cherng Sheu, Huang-Yi Huang, Chih-Wei Chang, Chi On Chui