Patents by Inventor Chih-Wei Chang

Chih-Wei Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11576279
    Abstract: A heat dissipation device is provided and includes a vapor chamber unit, a heat pipe set provided on an outer surface of the vapor chamber unit, a first fin set provided on the outer surface of the vapor chamber unit and sleeving the heat pipe set, and a second fin set stacked on the first fin set and sleeving the heat pipe set, where the fin arrangement direction of the first fin set is different from the fin arrangement direction of the second fin set.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: February 7, 2023
    Assignee: AURAS TECHNOLOGY CO., LTD.
    Inventors: Chih-Wei Chen, Cheng-Ju Chang, Jyun-Wei Huang
  • Publication number: 20230029739
    Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.
    Type: Application
    Filed: July 29, 2021
    Publication date: February 2, 2023
    Inventors: Chih-Chung Chang, Sung-En Lin, Chung-Ting Ko, You-Ting Lin, Yi-Hsiu Liu, Po-Wei Liang, Jiun-Ming Kuo, Yung-Cheng Lu, Chi On Chui, Yuan-Ching Peng, Jen-Hong Chang
  • Publication number: 20230036522
    Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.
    Type: Application
    Filed: July 30, 2021
    Publication date: February 2, 2023
    Inventors: Chih-Liang CHEN, Guo-Huei WU, Ching-Wei TSAI, Shang-Wen CHANG, Li-Chun TIEN
  • Patent number: 11567291
    Abstract: An optical system is provided and includes a fixed assembly, a movable element, a movable assembly, a driving module and a stopping assembly. The fixed assembly defines a main axis. The movable element is movable relative to the fixed assembly and is connected to a first optical element. The movable assembly is connected to the movable element. The driving module is configured to drive the movable assembly so as to drive the movable element to move relative to the fixed assembly. The stopping assembly is configured to limit the range of motion of the movable element.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: January 31, 2023
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Che-Wei Chang, Chih-Wen Chiang, Chen-Er Hsu, Fu-Yuan Wu, Shou-Jen Liu, Chih-Wei Weng, Mao-Kuo Hsu, Hsueh-Ju Lu, Che-Hsiang Chiu
  • Publication number: 20230027575
    Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.
    Type: Application
    Filed: January 21, 2022
    Publication date: January 26, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Huei LEE, Chun-Wei CHANG, Jian-Hong LIN, Wen-Hsien KUO, Pei-Chun LIAO, Chih-Hung NIEN
  • Publication number: 20230027120
    Abstract: An electronic package is provided, in which a carrier structure provided with electronic components is disposed onto an antenna structure, where a stepped portion is formed at an edge of the antenna structure, so that a shielding body is arranged along a surface of the stepped portion. Therefore, the shielding body only covers a part of the surface of the antenna structure to prevent the shielding body from interfering with operation of the antenna structure.
    Type: Application
    Filed: August 25, 2021
    Publication date: January 26, 2023
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Shao-Tzu Tang, Wen-Jung Tsai, Chih-Hsien Chiu, Ko-Wei Chang, Yu-Wei Yeh, Yu-Cheng Pai, Chuan-Yi Pan, Chi-Rui Wu
  • Publication number: 20230027552
    Abstract: A fluid immersion cooling system includes a fluid tank that contains a layer of a dual-phase coolant fluid and one or more layers of single-phase coolant fluids. The dual-phase and single-phase coolant fluids are immiscible, with the dual-phase coolant fluid having a lower boiling point and higher density than a single-phase coolant fluid. A substrate of an electronic system is submerged in the tank such that high heat-generating components are immersed at least in the layer of the dual-phase coolant fluid. Heat from the components is dissipated to the dual-phase coolant fluid to generate vapor bubbles of the dual-phase coolant fluid. The vapor bubbles rise to a layer of a single-phase coolant fluid that is above the layer of the dual-phase coolant fluid. The vapor bubbles condense to droplets of the dual-phase coolant fluid. The droplets fall down into the layer of the dual-phase coolant fluid.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Applicant: Super Micro Computer, Inc.
    Inventors: Yueh Ming LIU, Yu Hsiang HUANG, Yu Chuan CHANG, Tan Hsin CHANG, Hsiao Chung CHEN, Chia-Wei CHEN, Chih-Ta CHEN, Cheng-Hung LIN, Ming-Te HSU
  • Patent number: 11563001
    Abstract: A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: January 24, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lin-Yu Huang, Chiao-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Publication number: 20230020696
    Abstract: An anti-fuse memory cell includes a substrate, a gate dielectric layer over the substrate, a word line gate over the gate dielectric layer, a first implant region on a first side of the word line gate, a bit line contact plug over the first implant region, a second implant region on a second side of the word line gate opposite the first side of the word line gate, an oxidized region on the second implant region and having a convex upper surface and a source line gate over the convex upper surface of the oxidized region.
    Type: Application
    Filed: July 16, 2021
    Publication date: January 19, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Pin CHANG, Chien-Hung LIU, Chih-Wei HUNG
  • Publication number: 20230013953
    Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure, and the semiconductor structure. The method includes: providing a substrate having a connection hole thereon, annular protrusions and annular grooves alternately arranged along a direction parallel to a center line of the connection hole being provided on a hole wall of the connection hole; filling a barrier block in each of the annular grooves; removing the annular protrusions along a direction perpendicular to the hole wall of the connection hole; removing the barrier blocks; and forming a connection layer in the connection hole. After the annular protrusions are removed, roughness of the hole wall of the connection hole is reduced, such that a conductive seed layer is prevented from being broken, thereby avoiding generation of voids in the connection layer, and improving performance of the semiconductor structure.
    Type: Application
    Filed: September 27, 2022
    Publication date: January 19, 2023
    Inventor: CHIH-WEI CHANG
  • Publication number: 20230013764
    Abstract: Semiconductor devices including backside capacitors and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure, the front-side interconnect structure including a front-side conductive line; a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a backside conductive line, the backside conductive line having a line width greater than a line width of the front-side conductive line; and a first capacitor structure coupled to the backside interconnect structure.
    Type: Application
    Filed: March 1, 2022
    Publication date: January 19, 2023
    Inventors: Chih-Chao Chou, Yi-Hsun Chiu, Shang-Wen Chang, Ching-Wei Tsai, Chih-Hao Wang, Min Cao
  • Publication number: 20230011840
    Abstract: A chip bonding method includes the following operations. A first chip is provided, which includes a first contact pad including a first portion lower than a first surface of a first substrate and a second portion higher than the first surface of the first substrate to form the stepped first contact pad. A second chip is provided, which includes a second contact pad including a third portion lower than a third surface of a second substrate and a fourth portion higher than the third surface of the second substrate to form the stepped second contact pad. The first chip and the second chip are bonded. The first portion of the first chip contacts with the fourth portion of the second chip, and the second portion of the first chip contacts with the third portion of the second chip.
    Type: Application
    Filed: February 13, 2022
    Publication date: January 12, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Chih-Wei CHANG
  • Publication number: 20230009640
    Abstract: Semiconductor devices and methods are provided which facilitate performing physical failure analysis (PFA) testing from a backside of the devices. In at least one example, a device is provided that includes a semiconductor device layer including a plurality of diffusion regions. A first interconnection structure is disposed on a first side of the semiconductor device layer, and the first interconnection structure includes at least one electrical contact. A second interconnection structure is disposed on a second side of the semiconductor device layer, and the second interconnection structure includes a plurality of backside power rails. Each of the backside power rails at least partially overlaps a respective diffusion region of the plurality of diffusion regions and defines openings which expose portions of the respective diffusion region at the second side of the semiconductor device layer.
    Type: Application
    Filed: May 6, 2022
    Publication date: January 12, 2023
    Inventors: Chih-Chao CHOU, Yi-Hsun CHIU, Shang-Wen CHANG, Ching-Wei TSAI, Chih-Hao WANG
  • Publication number: 20230011710
    Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.
    Type: Application
    Filed: July 8, 2022
    Publication date: January 12, 2023
    Inventors: KUO-WEI CHI, CHUN-CHI YU, CHIH-WEI CHANG
  • Patent number: 11552084
    Abstract: Methods and devices including a plurality of memory cells and a first bit line connected to a first column of memory cells of the plurality of memory cells, and a second bit line connected to the first column of cells. The first bit line is shared with a second column of memory cells adjacent to the first column of memory cells. The second bit line is shared with a third column of cells adjacent to the first column of cells opposite the second column of cells.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: January 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ping-Wei Wang, Chih-Chuan Yang, Lien Jung Hung, Feng-Ming Chang, Kuo-Hsiu Hsu, Kian-Long Lim, Ruey-Wen Chang
  • Publication number: 20220416013
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor is provided. The MIM capacitor includes a substrate, a first metal layer, a deposition structure, a dielectric layer and a second metal layer. The first metal layer is disposed on the substate and has a planarized surface. The deposition structure is disposed on the first metal layer, and at least a portion of the deposition structure extends into the planarized surface, wherein the first metal layer and the deposition structure have the same material. The dielectric layer is disposed on the deposition structure. The second metal layer is disposed on the dielectric layer.
    Type: Application
    Filed: August 31, 2022
    Publication date: December 29, 2022
    Inventors: Bo-Wei HUANG, Chun-Wei KANG, Ho-Yu LAI, Chih-Sheng CHANG
  • Publication number: 20220406372
    Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.
    Type: Application
    Filed: March 18, 2022
    Publication date: December 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao PAO, Kian-Long LIM, Chih-Chuan YANG, Jui-Wen CHANG, Chao-Yuan CHANG, Feng-Ming CHANG, Lien-Jung HUNG, Ping-Wei WANG
  • Patent number: 11531524
    Abstract: In some embodiments, a method for generating a random bit is provided. The method includes generating a first random bit by providing a random number generator (RNG) signal to a magnetoresistive random-access memory (MRAM) cell. The RNG signal has a probability of about 0.5 to switch the resistive state of the MRAM cell from a first resistive state corresponding to a first data state to a second resistive state corresponding to a second data state. The first random bit is then read from the MRAM cell.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Chih-Hui Weng, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang, Chia-Hsiang Chen
  • Patent number: 11531057
    Abstract: The present disclosure relates to a through-silicon via (TSV) crack detecting apparatus, a detecting method, and a fabricating method of the semiconductor device. The TSV crack detecting apparatus includes a test TSV, a conductive liner, a second dielectric liner, a first contact, and a second contact. The test TSV is disposed within a semiconductor substrate, including a conductive channel and a first dielectric liner for isolating the conductive channel and the semiconductor substrate. The conductive liner surrounds the first dielectric liner. The second dielectric liner surrounds the conductive liner. The first contact is connected to the conductive channel. The second contact is connected to the conductive liner. A voltage difference between the first contact and the second contact is used to determine whether a TSV within a predetermined range to the test TSV has a crack based on a conductive state between the first contact and the second contact.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: December 20, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: You-Hsien Lin, Chih-Wei Chang
  • Patent number: 11532703
    Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Shang-Wen Chang, Yi-Hsun Chiu, Pei-Yu Wang, Ching-Wei Tsai, Chih-Hao Wang