Patents by Inventor Chih-Wei Hsiung

Chih-Wei Hsiung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130193511
    Abstract: A vertical transistor structure comprises a substrate, a plurality of pillars formed on the substrate and spaced from each other, a plurality of trenches each formed between two adjacent pillars, a protection layer formed on the surface of a first side wall and the surface of a second side wall of the trench, a first gate and a second gate respectively formed on the protection layer of the first side wall and the second side wall, and a separation layer covering a bottom wall of the trench. The present invention uses the separation layer functioning as an etch stopping layer to the first gate and the second gate while being etched. Further, thickness of the separation layer is used to control the distance between the bottom wall and the first and second gates and define widths of the drain and the source formed in the pillar via ion implantation.
    Type: Application
    Filed: January 26, 2012
    Publication date: August 1, 2013
    Inventors: Hsuan-Yu FANG, Wei-Chih Liu, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Chung-Yung Ai, Yu-Shan Hsu, Wei-Che Chang, Chun-Hua Huang, Kazuaki Takesako, Tomohiro Kadoya, Wen Kuei Hsu, Hirotake Fujita, Yukihiro Nagai, Chih-Wei Hsiung, Yoshinori Tanaka
  • Publication number: 20130157454
    Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Wei-Che CHANG, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
  • Patent number: 8461056
    Abstract: A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: June 11, 2013
    Assignee: Rexchip Electronics Corporation
    Inventors: Wei-Che Chang, Chun-Hua Huang, Chung-Yung Ai, Wei-Chih Liu, Hsuan-Yu Fang, Yu-Ling Huang, Meng-Hsien Chen, Chun-Chiao Tseng, Yu-Shan Hsu, Kazuaki Takesako, Hirotake Fujita, Tomohiro Kadoya, Wen Kuei Hsu, Chih-Wei Hsiung, Yukihiro Nagai, Yoshinori Tanaka
  • Patent number: 8437184
    Abstract: A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: May 7, 2013
    Assignee: Rexchip Electronics Corporation
    Inventor: Chih-Wei Hsiung
  • Publication number: 20130105890
    Abstract: A vertical non-dynamic RAM structure comprises a substrate, at least one bit line arranged on the substrate, a plurality of pillars spaced from each other and formed on the bit line with a plurality of troughs formed between them, a plurality of static storage elements respectively connected with the pillar, a plurality of gates respectively formed in one trough and independent to each other without connecting. A dielectric layer separates each gate from the neighboring pillar and the bit line. The present invention provides two independent gates functioning as transistors at two sides of each pillar to control the conduction state of the pillar. Therefore, the present invention needn't etch metal lines to fabricate gates and is thus free of the problem that the gates are hard to satisfy the requirement of smaller feature size.
    Type: Application
    Filed: October 27, 2011
    Publication date: May 2, 2013
    Inventor: Chih-Wei Hsiung
  • Patent number: 8431975
    Abstract: A back side illumination (BSI) image sensor includes at least one pixel. The pixel area includes a photo diode and a transfer transistor. The transfer transistor has a control electrode made of a gate poly and a gate oxide for receiving a control instruction, a first electrode coupled to the photo diode, and a second electrode, wherein an induced conduction channel of the transfer transistor partially surrounds a recessed space which is filled with the gate poly and the gate oxide of the transfer transistor.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: April 30, 2013
    Assignee: Himax Imaging, Inc.
    Inventors: Chih-Wei Hsiung, Fang-Ming Huang, Chung-Wei Chang
  • Patent number: 8367455
    Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.
    Type: Grant
    Filed: May 30, 2010
    Date of Patent: February 5, 2013
    Assignee: Himax Imaging, Inc.
    Inventors: Yu-Ping Hu, Chih-Wei Hsiung, Fang-Ming Huang, Chia-Chi Huang, Chung-Wei Chang
  • Patent number: 8357964
    Abstract: A three-dimensional dynamic random access memory with an ancillary electrode structure includes a substrate, at least one bit line formed on the substrate, at least one pillar element formed on a growth zone of the bit line, an ancillary electrode, a character line parallel with the substrate and perpendicular to the bit line, and at least one capacitor connecting to the pillar element. The bit line is formed on the substrate by doping and diffusing a doping element. The ancillary electrode is located on a separation zone of the bit line and adjacent to the pillar element. The character line is insulated from the ancillary electrode and incorporates with the bit line to output or input electronic data to the capacitor. Through the ancillary electrode, impedance of the bit line can be controlled to enhance conductivity of the bit line.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: January 22, 2013
    Assignee: Rexchip Electronics Corporation
    Inventors: Chih-Yuan Chen, Meng-Hsien Chen, Chih-Wei Hsiung
  • Publication number: 20120193691
    Abstract: A back side illumination (BSI) image sensor includes at least one pixel. The pixel area includes a photo diode and a transfer transistor. The transfer transistor has a control electrode made of a gate poly and a gate oxide for receiving a control instruction, a first electrode coupled to the photo diode, and a second electrode, wherein an induced conduction channel of the transfer transistor partially surrounds a recessed space which is filled with the gate poly and the gate oxide of the first transistor.
    Type: Application
    Filed: January 31, 2011
    Publication date: August 2, 2012
    Inventors: Chih-Wei Hsiung, Fang-Ming Huang, Chung-Wei Chang
  • Publication number: 20110291211
    Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.
    Type: Application
    Filed: May 30, 2010
    Publication date: December 1, 2011
    Inventors: Yu-Ping Hu, Chih-Wei Hsiung, Fang-Ming Huang, Chia-Chi Huang, Chung-Wei Chang
  • Patent number: 6033232
    Abstract: A method of fabricating a photodiode and at least one MOS device within a first active region and a second active region, respectively, of a substrate is disclosed. First, a gate structure is formed on the substrate within the second active region, and lightly-doped regions are formed by introducing first dopants into the substrate through the gate structure as masking. Then, a diffusion region is formed in the substrate within the first active region by ion implantation. Then, an insulating layer is formed to overlie the first and second active region, a portion of which within the second active region is thereafter patterned to sidewall spacers on the sidewalls of the gate structure. Subsequently, heavily-doped regions are formed by introducing second dopants throughout the second active region into the substrate by the gate structure and sidewall spacers as masking. In addition, the insulating layer can be thinned before the step of patterning the insulating layer to form the sidewall spacers is performed.
    Type: Grant
    Filed: October 14, 1998
    Date of Patent: March 7, 2000
    Assignee: Powerchip Semiconductor Corp.
    Inventors: James H. C. Lin, Chih-Wei Hsiung