Abstract: A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

Abstract: A flash memory with a self-aligned spilt gate and the methods for fabricating and operating the same are described. The flash cell consists of a substrate having a deep n-type well and a shallow p-type well in the deep n-type well therein, a control gate structure on the gate oxide layer located on the p-type shallow well, a floating gate on one sidewall of the control gate and over the substrate, a tunnel oxide layer between the control gate and the floating gate and between the floating gate and the substrate, a drain and a common source disposed beneath each side of the control gate in the substrate, wherein the depth of the drain and the common source are larger than the depth of the shallow p-type well, a pocket p-type well in the substrate around the drain and electrically connecting with the shallow p-type well.

Abstract: Dual-bit nitride read only memory (NROM) cell with parasitic amplifier and method of fabricating and reading the same. A NROM cell comprises a semiconductor substrate with a first well region having a conductive type opposite that of the substrate disposed therein. A second well region having a conductive type opposite to the first well region is disposed in the first well region. A gate dielectric layer is disposed over portions of the second well region, wherein the gate dielectric layer comprises a nitride layer. A conductive layer is disposed on the gate dielectric layer to form a gate. And, a pair of first doped regions having a conductive type opposite to the second well region are symmetrically disposed in the second well region of both sides of the gate, wherein one of the first doped regions, the second well region and the first well region constitute a parasitic current amplifier.

Abstract: A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.

Abstract: A method of manufacturing a flash memory is provided. A semiconductor substrate with a tunnel dielectric layer, a conductive layer and a mask layer sequentially formed thereon is provided. The mask layer, the conductive layer, the tunnel dielectric layer and the substrate are patterned to form a trench in the substrate. Thereafter, an insulating layer is formed inside the trench with the upper surface of the insulating layer at a level between the conductive layer and the substrate. A conductive spacer is formed on the sidewall of the mask layer and a portion of the conductive layer. The conductive layer and the conductive spacer together form a floating gate. The mask layer is removed and then an inter-gate dielectric layer is formed over the floating gate. A control gate is formed over the substrate.

Abstract: A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.

Abstract: A structure of a flash memory, having a deep P-well formed in an N-type substrate, an N-well formed in the deep P-well, a stacked gate structure formed on the substrate, an N-type source region and an N-type drain region formed in an N-well at two respective sides of the stacked gate, where the N-type source region is in electric contact with the N-well, a P-well formed in the N-well to encompass the N-type source region and to extend towards the N-type drain region through the portion under the stacked gate, and a contact window formed at the junction of the N-type source region and the P-well to electrically short circuit the N-type source region and the P-well. The flash memory uses F-N tunneling effect for programming and the channel F-N tunneling effect to perform the erase operation.

Abstract: A flash memory device includes a substrate having a trench, a deep N-type well region in the substrate, a stacked gate structure on the substrate, a first and a second spacer on a sidewall of the stacked gate, wherein the first spacer is connected with the top of the trench, a source region in the substrate under the first spacer, a drain region in the substrate under the second spacer, a P-type well region between the stacked gate and the deep N-type well region, wherein the junction between the two well regions is higher than the bottom of the trench, a doped region along the bottom and the sidewall of the trench, wherein this doped region is connected with the source region and isolates the P-type well region from the contact formed in the trench, the contact being electrically connected to the source region.

Abstract: A method of fabricating a trench flash memory device, where the method includes forming a patterned mask layer on the substrate and using it as the mask for form a trench in the substrate. Next, a source region is formed in the substrate near the bottom of the trench, followed by forming a tunnel oxide layer, a floating gate, a gate dielectric layer and a control in the trench. After removing the mask layer to expose the substrate, a drain region is further formed in the substrate. In this invention, since the trench flash memory device has a cylindrical shape with the tunnel oxide layer, the floating gate and the gate dielectric layer wrapping around the control gate, the overlap area between the floating gate and the control gate is increased, resulting in a higher gate coupling rate (GCR), a lower required operation voltage and a higher device operation speed and efficiency.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. Adrain is disposed in the p-well between the pair of selective gates.

Abstract: A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.

Abstract: A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.

Abstract: A split-gate flash memory structure. The flash memory structure mainly includes a substrate, a control gate over the substrate and a floating gate between the substrate and the control gate. A first side of the floating gate and the control gate are aligned. A second side of the floating gate protrudes beyond the control gate and has a corner with a sharp profile. The structure further includes spacers on the sidewalls of the control gate and the floating gate, a source region in the substrate on the first side of the floating gate, a drain region in the substrate on the second side of the floating gate and a select gate in the substrate between the spacers and the drain region. The sharp corner on the floating gate generates a higher electric field that speeds the erasure of data from the flash memory.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. A drain is disposed in the p-well between the pair of selective gates.

Abstract: A method of fabricating a memory device structure, where the method includes the steps of forming a tunnel oxide layer, a silicon nitride layer and a silicon oxide layer. A conductive layer is then formed on top of the silicon oxide. The conductive layer is then patterned to form a conductive gate layer. The silicon oxide layer is patterned during the same step of patterning the conductive layer, exposing the silicon nitride layer. Following that, a blanket dielectric layer is then formed on the substrate. This blanket dielectric layer is patterned with one etch step to form a spacer wall at the sides of the conductive gate layer.

Abstract: A single-poly EPROM and method for forming the same. The single-poly EPROM has an isolation region disposed in a substrate to define a striped active area. A deep n-well is located under the isolation region and the striped active area. A gate oxide layer is disposed on the substrate at the striped active area. A pair of striped selective gates perpendicular to the striped active area are disposed on the gate oxide layer and the isolation region. A pair of islanded floating gates are disposed on the gate oxide layer at the active area, with a gap between the pair of floating gates and the pair of selective gates. A striped p-well is disposed in the deep n-well between the pair of selective gates and below the pair of selective gates and portions of the pair of floating gates. A pair of sources are disposed on both sides of the p-well, and connected to each other through the deep n-well. A drain is disposed in the p-well between the pair of selective gates.

Abstract: A method for reading flash memory cell with SONOS structure is disclosed. The flash memory cell with SONOS structure includes a P-well in a substrate, a tunneling oxide layer on the substrate, a charge trapping layer on the tunneling oxide layer, a dielectric layer on the charge trapping layer, a gate conductive layer on the dielectric layer, and source and drain regions in the substrate adjacent to the gate conductive layer. The flash memory cell with SONOS structure is read by applying a positive voltage to the drain region, floating the source region, grounding the P-well to generate gate induced drain leakage current and determining the gate induced drain leakage from the drain region to read the data in the memory cell.

Abstract: A flash memory structure. The structure includes device isolation regions defined on an active area of a substrate, a deep well of first conductive type, stacked gate structures, a tunneling oxide layer, wells of second conductive type, sources and drains, wherein the aforementioned deep well of first conductive type is located in the active area and below the device isolation regions. The aforementioned wells of second conductive type are formed in the area corresponding to the drains and below the device isolation regions between the adjacent stacked gate structures. The aforementioned sources and drains are in the active areas located on both sides of the control gates, wherein the drains are enclosed by the wells of second conductive type; and the sources are located on both sides of the wells of second conductive type and electrically connected with each other via the deep well of first conductive type.

Abstract: A structure of a flash memory device. The flash memory comprises a deep n-well formed in a substrate, a p-well in the deep n-well, a stacked gate structure on the substrate, source and drain regions in the substrate at two respective sides of the stacked gate, an n-well extending from the drain region to a position under the stacked-gate structure, an n− pocket doped region under the stacked-gate structure and connected between the n-well and the source region. The flash memory uses avalanche induced hot electron injection for programming, and the F-N tunneling effect to perform erase operation.

Abstract: A light receiving circuit of a laser range finder comprises a photo-sensitive element, a conversion resistance amplifying loop, a main amplification loop, and a one shot circuit. The photo-sensitive element converts a light signal into a current signal. The conversion resistance amplifying loop is connected with the photo-sensitive element for converting the current signal into a voltage signal. The main amplification loop is connected with the conversion resistance amplifying loop for amplifying the voltage signal. The one shot loop is connected with the main amplification loop for shaping the voltage signal into a digital signal by which the range-finding computation is accomplished by the laser range finder.