Patents by Inventor Chih-Wei Lin

Chih-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200381325
    Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.
    Type: Application
    Filed: May 31, 2019
    Publication date: December 3, 2020
    Inventors: Tzu-Sung Huang, Ming Hung Tseng, Yen-Liang Lin, Hao-Yi Tsai, Chi-Ming Tsai, Chung-Shi Liu, Chih-Wei Lin, Ming-Che Ho
  • Publication number: 20200373215
    Abstract: A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chih-Wei Wu, Szu-Wei Lu, Jing-Cheng Lin
  • Publication number: 20200368229
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 26, 2020
    Applicant: AbbVie Inc.
    Inventors: Christine Collins, Bo Fu, Abhishek Gulati, Jens Kort, Matthew Kosloski, Yang Lei, Chih-Wei Lin, Ran Liu, Federico Mensa, Iok Chan Ng, Tami Pilot-Matias, David Pugatch, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhen Zhang
  • Publication number: 20200371425
    Abstract: In a method of manufacturing a photo mask, a resist layer is formed over a mask blank, which includes a mask substrate, a phase shift layer disposed on the mask substrate and a light blocking layer disposed on the phase shift layer. A resist pattern is formed by using a lithographic operation. The light blocking layer is patterned by using the resist pattern as an etching mask. The phase shift layer is patterned by using the patterned light blocking layer as an etching mask. A border region of the mask substrate is covered with an etching hard cover, while a pattern region of the mask substrate is opened. The patterned light blocking layer in the pattern region is patterned through the opening of the etching hard cover. A photo-etching operation is performed on the pattern region to remove residues of the light blocking layer.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chun-Chieh TIEN, Cheng-Hsuen CHIANG, Chih-Ming CHEN, Cheng-Ming LIN, Yen-Wei HUANG, Hao-Ming CHANG, Kuo-Chin LIN, Kuan-Shien LEE
  • Publication number: 20200373401
    Abstract: Semiconductor device structures comprising a gate structure having different profiles at different portions of the gate structure are provided. In some examples, a semiconductor device includes a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.
    Type: Application
    Filed: August 13, 2020
    Publication date: November 26, 2020
    Inventors: Chih Ping Wang, Chao-Cheng Chen, Jr-Jung Lin, Chi-Wei Yang
  • Patent number: 10847460
    Abstract: Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided. An example method for fabricating a conductive interconnection layer of an integrated circuit may include: patterning a conductive connector portion on the conductive interconnection layer of the integrated circuit using extreme ultraviolet (EUV) lithography, wherein the conductive connector portion is patterned to extend across multiple semiconductor structures in a different layer of the integrated circuit; and cutting the conductive connector portion into a plurality of conductive connector sections, wherein the conductive connector portion is cut by removing conductive material from the metal connector portion at one or more locations between the semiconductor structures.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chih-Liang Chen, Cheng-Chi Chuang, Chih-Ming Lai, Chia-Tien Wu, Charles Chew-Yuen Young, Hui-Ting Yang, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shun Li Chen, Shih-Wei Peng, Tien-Lu Lin
  • Patent number: 10846114
    Abstract: A virtual time control apparatus, method, and non-transitory computer readable storage medium thereof are provided. The virtual time control apparatus includes a system timer, a real time clock, and a processing unit, wherein the processing unit is electrically connected to the system timer and the real time clock. The system timer has an original timer period, while the real time clock has an original tick period. The processing unit executes a hypervisor. The hypervisor generates a virtual timer period according to an adjustment ratio and the original timer period. The hypervisor generates a virtual tick period according to the adjustment ratio and the original tick period.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: November 24, 2020
    Assignee: Institute For Information Industry
    Inventors: Sheng-Hao Wang, Jian-De Jiang, Chin-Wei Tien, Chih-Hung Lin
  • Publication number: 20200365578
    Abstract: An ESD circuit is connected between an I/O pad and a first node. The ESD circuit includes a bi-directional buck circuit, a triggering circuit and a discharging circuit. The bi-directional buck circuit includes a forward path and a reverse path. The forward path and the reverse path are connected between the I/O pad and a second node. The triggering circuit is connected between the second node and the first node. The discharging circuit is connected between the second node and the first node, and connected with the triggering circuit. When the I/O pad receives negative ESD zap, the ESD current flows from the first node to the I/O pad through the discharging circuit and the reverse path. When the I/O pad receives positive ESD zap, the ESD current flows from the I/O pad to the first node through the forward path and the discharging circuit.
    Type: Application
    Filed: March 4, 2020
    Publication date: November 19, 2020
    Inventors: Yun-Jen TING, Chih-Wei LAI, Yi-Han WU, Kun-Hsin LIN, Hsin-Kun HSU
  • Patent number: 10840111
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 10832999
    Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Hung Lin, Chih-Wei Lin, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200350197
    Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Wei Lin, Hui-Min Huang, Ai-Tee Ang, Yu-Peng Tsai, Ming-Da Cheng, Chung-Shi Liu
  • Publication number: 20200350250
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Pochun WANG, Ting-Wei CHIANG, Chih-Ming LAI, Hui-Zhong ZHUANG, Jung-Chan YANG, Ru-Gun LIU, Ya-Chi CHOU, Yi-Hsiung LIN, Yu-Xuan HUANG, Yu-Jung CHANG, Guo-Huei WU, Shih-Ming CHANG
  • Patent number: 10825385
    Abstract: An apparatus receives current image frame data and data relating to at least one previous image frame for an electronic display. One or more parameters related to hysteresis of transistors in the electronic display are sensed. A correlation device, such as a look-up table, receives the sensed parameter or parameters and the data relating to one or more image frames, and uses this information, at least in part, to output an appropriate compensation signal for the current image frame data. The compensated current image frame data may then be supplied to the electronic display to reduce or eliminate the effects of hysteresis on the displayed image.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: November 3, 2020
    Assignee: Apple Inc.
    Inventors: Chaohao Wang, Chih-Wei Yeh, Chin-Wei Lin, Hung Sheng Lin, Hyunwoo Nho, Injae Hwang, Jie Won Ryu, Junhua Tan, Paolo Sacchetto, Rui Zhang, Shengkui Gao, Sun-Il Chang, Wei H. Yao, Howard H. Tang
  • Patent number: 10825724
    Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Yu-Hung Lin, Sheng-Hsuan Lin, Chih-Wei Chang, You-Hua Chou
  • Publication number: 20200338796
    Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.
    Type: Application
    Filed: April 29, 2019
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Feng Weng, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Sheng-Hsiang Chiu, Yao-Tong Lai, Chia-Min Lin
  • Patent number: 10818614
    Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Ching-Hua Hsieh, Chung-Shi Liu, Chih-Wei Lin, Hao-Cheng Hou, Jung-Wei Cheng
  • Patent number: 10820423
    Abstract: A fabrication method of a circuit includes drilling holes in a substrate, so as to form a plurality of first opening holes and second opening holes in the substrate. A cover film is attached onto the substrate, so as to cover the first opening holes and the second opening holes. A portion of the cover film covering the first opening holes is removed, so as to expose the first opening holes. The first opening holes are filled.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: October 27, 2020
    Assignee: Gold Circuit Electronics Ltd.
    Inventors: Chih-Hai Yu, Kuo-Wei Lo, Cheng-Hsiao Lin
  • Patent number: 10818515
    Abstract: The present disclosure provides an electronic package and a method for fabricating the same. A protective layer is formed on a carrier of the electronic component. The electronic component and the protective layer are covered by a covering layer. A through hole is formed in the covering layer and extends through the protective layer, such that a portion of a surface of the carrier is exposed to the through hole. A conductive structure is disposed in the through hole and electrically connected with the carrier. Through the formation of the protective layer, the buffering effect of the protective layer can prevent the laser from directly burning through the covering layer and the protective layer to avoid damages to the carrier.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: October 27, 2020
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yu-Wei Yeh, Yen-Hung Lin, Chih-Yi Liao, Chih-Hsien Chiu
  • Publication number: 20200335597
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed over the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below the gate structure. The semiconductor device structure further includes two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. The first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall. The gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Min-Hsiu HUNG, Yi-Hsiang CHAO, Kuan-Yu YEH, Kan-Ju LIN, Chun-Wen NIEH, Huang-Yi HUANG, Chih-Wei CHANG, Ching-Hwanq SU
  • Publication number: 20200330460
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: August 30, 2018
    Publication date: October 22, 2020
    Applicant: AbbVie Inc.
    Inventors: Christine Collins, Emily O. Dumas, Bo Fu, Abhishek Gulati, Yiran Bonnie Hu, Jens Kort, Matthew Kosloski, Preethi Krishnan, Yang Lei, Chih-Wei Lin, Ran Liu, Frederico Mensa, Iok Chan Ng, Tami Pilot-Matias, David Pugatch, Susan Rhee, Nancy S. Shulman, Roger Trinh, Rolando M. Viani, Stanley Wang, Zhenzhan Zhang