Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.

Abstract: A device may include a first package and a second package where the first package has a warped shape. First connectors attached to a redistribution structure of the first package include a spacer embedded therein. Second connectors attached to the redistribution structure are fee from the spacer, the spacer of the first connectors keeping a minimum distance between the first package and the second package during attaching the first package to the second package.

Abstract: A method for data transmission between a sensor device and an electronic device includes: broadcasting, by the sensor device, a beacon dataset and a sensor dataset associated with the beacon dataset; in receipt of the beacon dataset, determining, by the electronic device, whether to receive the sensor dataset associated with the beacon dataset; and when it is determined to receive the sensor dataset associated with the beacon dataset, operating, by the electronic device, in a scan mode so as to receive the sensor dataset associated with the beacon dataset.

Abstract: A device for testing a group of radio-frequency (RF) chip modules and a method for using the same is disclosed. The device includes a signal analyzer, a power divider, control ICs, a signal controller, and a power combiner. The power divider receives an RF signal and transmits RF input signals to the RF chip modules and the control ICs in response to the RF signal. The signal controller controls each control IC to adjust at least one of the power and the phase of the corresponding RF input signal, thereby generating an RF output signal. The power combiner receives the RF output signal from each control IC to generate a test signal. The signal analyzer receives the test signal and obtains RF properties corresponding to at least one of the power and the phase of each RF output signal.

Abstract: An optical electrical connector includes a casing, a printed circuit board, an electronic chip, a photoelectric conversion component, and a heat sink device. The casing includes an electrical port and an optical port. A receiving space is defined between the electrical port and the optical port. The printed circuit board extends longitudinally along a first direction. The printed circuit board includes a main body portion located in the receiving space and a front end portion exposed in the electrical port. The electronic chip, the photoelectric conversion component and the heat sink device are all accommodated in the receiving space. The electronic chip and the photoelectric conversion component are not only disposed on the printed circuit board, but also electrically connected to the printed circuit board. The heat sink device is disposed on the casing and faces the electronic chip for conducting the heat accumulated on the electronic chip.

Abstract: A system for testing antenna-in-package (AiP) modules and a method for using the same is disclosed. Firstly, AiP modules respectively receive RF signals from a testing transmitting antenna. Then, at least one of the power and the phase of each of the RF signals is adjusted to generate modulated RF amplified signals as recognition tags with difference. The RF amplified signals are received from each control integrated circuit (IC) and the power of the modulated RF amplified signals is summed to generate a net mixed test signal. Finally, the test signal is received and RF properties corresponding to at least one of the power and the phase of each of the RF amplified signals as recognition tags are obtained. The method can simultaneously test a plurality of AiP modules to shorten the test time.

Abstract: Systems and methods for monitoring the quality of a surface treatment applied to an article in a manufacturing process are provided. A surface treatment may be applied to at least a portion of an article. A thermal profile of the article may be obtained and used to determine temperature indications of different regions of the article to which the surface treatment has been applied. A standard model of the article may be obtained that includes model regions having model temperature ranges. The temperature indications of the article can be compared with the model temperature ranges to determine if any temperature indications are outside of a corresponding model temperature range. The article may be a shoe part. The surface treatments may include the application of heat, plasma, dye, paint, primer, and/or the application of other materials, substances, and/or processes.

Abstract: A method includes forming a first metal mesh over a carrier, forming a first dielectric layer over the first metal mesh, and forming a second metal mesh over the first dielectric layer. The first metal mesh and the second metal mesh are staggered. The method further includes forming a second dielectric layer over the second metal mesh, attaching a device die over the second dielectric layer, with the device die overlapping the first metal mesh and the second metal mesh, encapsulating the device die in an encapsulant, and forming redistribution lines over and electrically connecting to the device die.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a light-collimating layer. The substrate has a plurality of pixels. The light-collimating layer is disposed on the substrate, and the light-collimating layer includes a transparent material layer, a first light-shielding layer, a second light-shielding layer and a plurality of transparent pillars. The transparent material layer covers the pixels. The first light-shielding layer is disposed on the substrate and the first light-shielding layer has a plurality of holes corresponding to the pixels. The second light-shielding layer is disposed on the first light-shielding layer. The transparent pillars are disposed in the second light-shielding layer.

Abstract: A restorable anti-glare film is disclosed. The restorable anti-glare film comprises a transparent substrate and a restorable anti-glare layer comprising a siloxane-containing urethane (meth)acrylate copolymer and a plurality of (meth)acrylic resin particles formed on the transparent substrate, wherein the weight average molecular weight (Mw) of the siloxane-containing urethane (meth)acrylate copolymer is between 4,000 and 60,000, and the (meth)acrylic resin particles have a 30% compressive strength of 14.7 MPa to 49 MPa and a recovery rate of more than 22%. The present restorable anti-glare film can provide a scratch-restorability and a stable and reliable anti-glare property.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: Package structures and methods for forming the same are provided. The method includes forming a passivation layer having an opening and forming a first seed layer in the opening. The method further includes filling the opening with a conductive layer over the first seed layer and bonding an integrated circuit die to the conductive layer over a first side of the passivation layer. The method further includes removing a portion of the first seed layer to expose a top surface of the conductive layer and to partially expose a first sidewall of the passivation layer from a second side of the passivation layer and forming a second seed layer over the top surface of the conductive layer and over the first sidewall of the passivation layer.

Abstract: The present invention provides an adaptive proximity sensing device, which can adjust the lighting power of a light-emitting element according to the sensed intensity to extends the sensing range. Further, the device can normalize the final sensed intensity to return the normal sensed intensity. Moreover, the uses a linear model of the normal sensed intensity and the distance, so the device can quickly determine the distance of the object.

Abstract: This invention provides an earphone with a low light transmittance and a non-porous sensor cover. Covering the sensing cover on the proximity sensing device can reduce the interference of most of the ambient light and improve measurement accuracy.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Abstract: A package structure including a substrate, a first semiconductor element disposed on and electrically connected with the substrate, a second semiconductor element disposed on and electrically connected with the substrate and a molding layer disposed over the substrate and covering at least a top surface of the substrate. The second semiconductor element and the first semiconductor element perform different functions. The molding layer encapsulates the second semiconductor element and wraps around sidewalls of the first semiconductor element. A top surface of the molding layer is higher than a top surface of the first semiconductor element. The molding layer has an opening extending from the top surface of the molding layer to the top surface of the first semiconductor element, so that the top surface of the first semiconductor element is exposed.

Abstract: This invention provides an earphone with a low light transmittance and a non-porous sensor cover. Covering the sensing cover on the proximity sensing device can reduce the interference of most of the ambient light and improve measurement accuracy.

Abstract: A package structure includes a circuit substrate, a package element and a molding layer. The package element is disposed on the circuit substrate and is electrically connected with the circuit substrate. The molding layer is disposed over the circuit substrate and covers at least a top surface of the circuit substrate. The molding layer includes a first portion wrapping around sidewalls of the package element and having a first thickness, and a second portion surrounding the first portion and connected with the first portion. The first thickness of the first portion is larger than a second thickness of the second portion. A top surface of the first portion of the molding layer is higher than a top surface of the package element.