Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.

Abstract: A computing system includes a chassis, a water circulation network coupled to the chassis, a power distribution network coupled to the chassis, and one or more sleds removably coupled to the chassis. The water circulation network includes a cold water distribution network and a hot water collection network. Each sled of the one or more sleds includes a corresponding cold plate. Each sled is configured to slide along the chassis in two slide directions including a slide-close direction to reach a closed position and a slide-open direction to vacate the closed position. When in the closed position, each sled is configured to (a) bridge the hot water collection network and the cold water distribution network via the corresponding cold plate and (b) couple to the power distribution network.

Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.

Abstract: A cleaning apparatus for cleaning a surface of a photomask includes a housing defining a chamber, a photomask holder disposed within the chamber, and a gas dispenser disposed within the chamber to direct gas toward the photomask holder. The gas dispenser has two or more gas dispensing outlets. A driver is coupled to at least one of the photomask holder or the gas dispenser to establish relative movement between the photomask holder and the gas dispenser.

Abstract: A semiconductor arrangement includes a heat source above an interconnect layer and below a heat conductor. The heat conductor is coupled to a heat sink by a thermally conductive bonding layer. Heat from the heat source is conducted through the heat conductor in a direction opposite the direction of the interconnect layer, through the thermally conductive bonding layer, and to a heat sink. The heat conductor includes an arrangement of dielectric layers, dummy metal layers, and dummy VIA layers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.

Abstract: A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

Abstract: A method for cleaning a reflective photomask, a method of manufacturing a semiconductor structure, and a system for forming a semiconductor structure are provided. The system for forming a semiconductor structure includes a photomask comprises a photomask substrate and a pellicle; an exposure tool configured to perform an exposure operation to transfer a pattern of the photomask to a semiconductive substrate, and a cleaning tool configured to perform a cleaning operation on the photomask. The cleaning tool includes a processing chamber configured to accommodate the photomask for a cleaning operation, and a hydrogen radical producer configured to produce hydrogen radicals into the processing chamber and having the hydrogen radicals reacting with contaminants attached on the photomask. The pellicle is attached on the photomask substrate during the cleaning operation.

Abstract: A semiconductor device includes a first and a second semiconductor fins extending along a first direction; an isolation region disposed between respective lower portions of the first and second semiconductor fins; a dielectric structure disposed between the first and the second semiconductor fins and above the isolation region, with a bottom surface aligned with a top surface of the isolation region; a gate isolation structure vertically disposed above the dielectric structure; and a metal gate layer extending along a second direction perpendicular to the first direction. The metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure separates the first and second portions of the metal gate layer from each other and includes a top portion vertically extending above the dielectric structure and a bottom portion extending into the dielectric structure.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: One or more computer processors determine a runtime feature set for a first container, wherein the runtime feature set includes aggregated temporally collocated container behavior. The one or more computer processors cluster the first container with one or more peer containers or peer pods based on a shared container purpose, similar container behaviors, and similar container file structure. The one or more computer processors determine an additional runtime feature set for each peer container. The one or more computer processors calculate a variance between the first container and each peer container. The one or more computer processors, responsive to the calculated variance exceeding a variance threshold, identify the first container as anomalous.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.

Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.

Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.

Abstract: One or more embodiments of the present disclosure describe an artificial intelligence assisted substrate defect repair apparatus and method. The AI assisted defect repair apparatus employs an object detection algorithm. Based on the plurality of images taken by detectors located at different respective positions, the detectors capture various views of an object including a defect. The composition information as well as the morphology information (e.g., shape, size, location, height, depth, width, length, or the like) of the defect and the object are obtained based on the plurality of images. The object detection algorithm analyzes the images and determines the type of defect and the recommends a material (e.g., etching gas) and the associated information (e.g., supply time of the etching gas, flow rate of the etching gas, etc.) for fixing the defect.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.