Abstract: An integrated circuit includes a first-voltage power rail and a second-voltage power rail in a first connection layer, and includes a first-voltage underlayer power rail and a second-voltage underlayer power rail below the first connection layer. Each of the first-voltage and second-voltage power rails extends in a second direction that is perpendicular to a first direction. Each of the first-voltage and second-voltage underlayer power rails extends in the first direction. The integrated circuit includes a first via-connector connecting the first-voltage power rail with the first-voltage underlayer power rail, and a second via-connector connecting the second-voltage power rail with the second-voltage underlayer power rail.

Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A conductive region is disposed in the polymer region and electrically coupled to the redistribution line. The conductive region includes a second flat top surface not higher than the first flat top surface.

Abstract: A power dividing and combining device comprising a resonance body, a plurality of circuit boards, an upper cover and a lower cover is provided. The resonance body comprises a solid conductive body, a plurality of first dividing elements, a plurality of second dividing elements, a signal-receiving end and a signal-transmitting end. The solid conductive body has a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connecting the first surface and the second surface. The first dividing elements are disposed on the first surface and separate a plurality of first resonance channels on the first surface. The first resonance channels intersect at a first common region on the first surface. The second dividing elements are disposed on the second surface and separate a plurality of second resonance channels on the second surface. The second resonance channels intersect at a second common region on the second surface.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: A package structure is provided. The package structure includes a first die and a second die, a dielectric layer, a bridge, an encapsulant, and a redistribution layer structure. The dielectric layer is disposed on the first die and the second die. The bridge is electrically connected to the first die and the second die, wherein the dielectric layer is spaced apart from the bridge. The encapsulant is disposed on the dielectric layer and laterally encapsulating the bridge. The redistribution layer structure is disposed over the encapsulant and the bridge. A top surface of the bridge is in contact with the RDL structure.

Abstract: A fastener is adapted for assembling a first housing to a second housing. The first housing is provided with a protruding portion and a buckling portion, and the second housing has a first surface, a second surface, and a through hole. The fastener includes a first portion, at least one connecting portion, at least two elastic portions, and a second portion. The first portion movably abuts against the first surface and has a first opening. The connecting portion is accommodated in the through hole. One end of the connecting portion is connected to the first portion. The connecting portion is spaced apart from an inner edge of the second housing by a gap. The two elastic portions inclinedly extend into the first opening. The second portion movably abuts against the second surface and is disposed at the another end of the connecting portion.

Abstract: A method for determining a standard depth value of a marker includes obtaining a maximum depth value of the marker. A reference depth value of the marker is obtained based on a depth image of the marker, and a Z-axis coordinate value of the marker is obtained based on a color image of the marker. When the reference depth value and the Z-axis coordinate value are both less than the maximum depth value, and a difference between the reference depth value and the Z-axis coordinate value is not greater than 0, the depth reference value is set as the standard depth value of the marker; and when the difference is greater than 0, the Z-axis coordinate value is set as the standard depth value of the marker.

Abstract: A fish identification method is provided. The fish identification method includes capturing an image through a processor, wherein the image includes a fish image. The fish identification method includes identifying a plurality of feature points of the fish image through a coordinate detection model and obtaining a plurality of sets of feature-point coordinates. Each of the plurality of sets of feature-point coordinates corresponds to each of the plurality of feature points. The fish identification method further includes calculating a body length or an overall length of the fish image according to the plurality of sets of feature-point coordinates of the image.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.

Abstract: An embodiment composite material for semiconductor package mount applications may include a first component including a tin-silver-copper alloy and a second component including a tin-bismuth alloy or a tin-indium alloy. The composite material may form a reflowed bonding material having a room temperature tensile strength in a range from 80 MPa to 100 MPa when subjected to a reflow process. The reflowed bonding material may include a weight fraction of bismuth that is in a range from approximately 4% to approximately 15%. The reflowed bonding material may an alloy that is solid solution strengthened by a presence of bismuth or indium that is dissolved within the reflowed bonding material or a solid solution phase that includes a minor component of bismuth dissolved within a major component of tin. In some embodiments, the reflowed bonding material may include intermetallic compounds formed as precipitates such as Ag3Sn and/or Cu6Sn5.

Abstract: A system for manufacturing an integrated circuit includes a processor coupled to a non-transitory computer readable medium configured to store executable instructions. The processor is configured to execute the instructions for generating a layout design of the integrated circuit that has a set of design rules. The generating of the layout design includes generating a set of gate layout patterns corresponding to fabricating a set of gate structures of the integrated circuit, generating a cut feature layout pattern corresponding to a cut region of a first gate of the set of gate structures of the integrated circuit, generating a first conductive feature layout pattern corresponding to fabricating a first conductive structure of the integrated circuit, and generating a first via layout pattern corresponding to a first via. The cut feature layout pattern overlaps a first gate layout pattern of the set of gate layout patterns.

Abstract: A method for manufacturing a nanosheet semiconductor device includes forming a poly gate on a nanosheet stack which includes at least one first nanosheet and at least one second nanosheet alternating with the at least one first nanosheet; recessing the nanosheet stack to form a source/drain recess proximate to the poly gate; forming an inner spacer laterally covering the at least one first nanosheet; and selectively etching the at least one second nanosheet.

Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: An antenna structure includes a first resonant unit and a second resonant unit. The first resonant unit is configured to transmit an input signal as a first wireless signal. The second resonant unit is configured to transmit the input signal as a second wireless signal. The first resonant unit and the second resonant unit have a substantially identical operating band, and the first resonant unit and the second resonant unit are a single continuous metal structure.

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.