Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.

Abstract: The present invention provides an optical sensor package assembly. The light shield is arranged in the groove of a package housing above the photosensitive chip. The connection wires between the substrate, the light emitting unit and the photosensitive chip can be printed or disposed on the surface of the substrate. Further, a distance between the photosensitive element and the chip edge is designed to reduce or avoid side leakage interference.

Abstract: A resin composition includes 20 parts by weight to 45 parts by weight of a phosphorus-containing bismaleimide and 100 parts by weight of a thermosetting resin, wherein the phosphorus-containing bismaleimide has a structure of Formula (I); the thermosetting resin is selected from a vinyl-containing polyphenylene ether resin, a maleimide resin, a polyolefin resin, a prepolymer of maleimide resin, and a combination thereof. The resin composition may be used to make a prepreg, a resin film, a laminate or a printed circuit board, and at least one of the following properties can be improved, including flame retardancy, outgassing properties, arc resistance, copper foil peeling strength, X-axis coefficient of thermal expansion, glass transition temperature and water absorption rate.

Abstract: A semiconductor package includes a first integrated circuit and a first waveguide. The first integrated circuit includes an optical coupler. The first waveguide is optically coupled to the optical coupler. In some embodiments, the first waveguide protrudes beyond the optical coupler. In some embodiments, the first waveguide is partially overlapped with the optical coupler.

Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

Abstract: The present invention is to provide an anti-glare film. The anti-glare film comprises a polyethylene terephthalate (PET) substrate and an anti-glare layer formed on a surface of the PET substrate, wherein the anti-glare coating layer comprises 75 to 90 weight parts of an acrylic-based resin, 0.01 to 10 weight parts of silica nanoparticles 5 to 20 weight parts of organic microparticles and 0.05 to 2 weight parts of leveling agent. The anti-glare film has a total haze ranging between 35% and 50%, a surface haze ranging between 10% and 15% and a gloss at a viewing angle of 60 degrees between 30% and 50% thereof. The anti-glare film can provide satisfactory anti-glare properties, high precision, surface fineness, no flicker, good visibility and also fine adhesion between layers.

Abstract: A package structure includes a first redistribution layer, a semiconductor die, and through vias. The first redistribution layer includes dielectric layers, first conductive patterns, and second conductive patterns. The dielectric layers are located in a core region and a peripheral region of the first redistribution layer. The first conductive patterns are embedded in the dielectric layers in the core region, wherein the first conductive patterns are arranged in the core region with a pattern density that gradually increases or decreases from a center of the core region to a boundary of the core region. The second conductive patterns are embedded in the dielectric layers in the peripheral region. The semiconductor die is disposed on the core region over the first conductive patterns. The through vias are disposed on the peripheral region and electrically connected to the second conductive patterns.

Abstract: A composite film for use in an LED wafer-level packaging process to facilitate adhesion of an LED wafer to a carrier and an LED wafer-level packaging process carried out with a heating process are introduced. The composite film includes a substrate including a first surface and a second surface; a heat-resisting pressure-sensing adhesive formed on the first surface of the substrate to allow the LED wafer to be adhered to the substrate; and a heat-resisting thermally-visbreaking pressure-sensing adhesive formed on the second surface of the substrate to allow the substrate to be adhered to the carrier. The heat-resisting thermally-visbreaking pressure-sensing adhesive undergoes the heating process to reduce its adhesiveness strength; thus, upon completion of the LED wafer-level packaging process, the carrier can be detached from the composite film easily.

Abstract: A molding apparatus is configured for molding a semiconductor device and includes a lower mold and an upper mold. The lower mold is configured to carry the semiconductor device. The upper mold is disposed above the lower mold for receiving the semiconductor device and includes a mold part and a dynamic part. The mold part is configured to cover the upper surface of the semiconductor device. The dynamic part is disposed around a device receiving region of the upper mold and configured to move relatively to the mold part. A molding method and a molded semiconductor device are also provided.

Abstract: A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

Abstract: The present invention proposes a chip reliability test assembly, which comprises a motherboard and a daughter board. The motherboard is used to support the chips during an aging acceleration process at high temperature. The daughter board is used to measure the electricity of chip after the aging acceleration process. Each chip holder is removable off the motherboard. The daughter board does not go through the aging acceleration process and can be reusable.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The gate stack includes a gate dielectric layer and a work function layer. The gate dielectric layer is between the semiconductor substrate and the work function layer. The semiconductor device structure also includes a halogen source layer. The gate dielectric layer is between the semiconductor substrate and the halogen source layer.

Abstract: A fingerprint sensor package and method are provided. Embodiments include a sensor and a sensor surface material encapsulated within the fingerprint sensor package. An array of electrodes of the sensor are electrically connected using through vias that are located either in the sensor, in connection blocks separated from the sensor, or through connection blocks, or else connected through other connections such as wire bonds. A high voltage die is attached in order to increase the sensitivity of the fingerprint sensor.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: The present invention provides a light sensor with dark current elimination. A dark current from a covered photodiode and a sensed current from a photodiode are respectively transformed to a dark voltage and a sensed voltage by a controlled integration circuit. A reverse capacitor receives the dark voltage and the sensed voltage to cancel out for each other, and outputs a corrected sensing voltage.

Abstract: A semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a waveguide. The photonic integrated circuit includes an optical coupler. The electronic integrated circuit is disposed aside the photonic integrated circuit. The waveguide is optically coupled to the optical coupler, wherein the waveguide is disposed at an edge of the photonic integrated circuit and protrudes from the edge of the photonic integrated circuit.

Abstract: A system includes a plurality of semiconductor processing tools; a carrier purge station; a carrier repair station; and an overhead transport (OHT) loop for transporting one or more substrate carriers among the plurality of semiconductor processing tools, the carrier purge station, and the carrier repair station. The carrier purge station is configured to receive a substrate carrier from one of the plurality of semiconductor processing tools, purge the substrate carrier with an inert gas, and determine if the substrate carrier needs repair. The carrier repair station is configured to receive a substrate carrier to be repaired and replace one or more parts in the substrate carrier.

Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

Abstract: A formable stopper applied to a fixing structure comprises a body having an assembly hole or an assembly section. The assembly hole or the assembly section includes a placement portion and an assembly portion. The assembly portion is in communication with or connected to the placement portion, or the placement portion is the assembly portion. The formable stopper further comprises a formable body. The formable body is adapted to be extruded, placed, or fitted into the placement portion, and extruded, placed, or fitted into the assembly portion, so as to form an interference structure or to form an interference force for preventing or avoiding the formable body from falling out of the assembly hole.