Abstract: An aerosol generating apparatus includes a vial, a cap assembly and a receptacle. The vial stores liquid medicament and includes a puncturable seal held in position by a retaining ring. The cap assembly includes an actuator with an interior bore extending therethrough, a perforated membrane coupled to the actuator, a fastener and a first mating element. The fastener is adapted to detachably secure the cap assembly to the vial such that the perforated membrane aligns with the puncturable seal. The receptacle receives the cap assembly with the vial. The receptacle includes a driving element and a second mating element capable of mating with the first mating element. The driving element aligns and communicates with the perforated membrane when the receptacle engages the cap assembly. The actuator pierces the puncturable seal to displace the liquid medicament through the interior bore to the perforated membrane and the driving element to generate aerosol.

Abstract: A method of fabricating an MRAM device includes forming a bottom electrode over a semiconductor substrate, forming a magnetic tunnel junction (MTJ) structure on the bottom electrode, and forming a top electrode on the MTJ structure. The method also includes forming spacers on sidewalls of the top electrode and the MTJ structure, and depositing a first dielectric layer to surround the spacers. The method further includes selectively depositing a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the method includes depositing a second dielectric layer on the patterned etch stop layer and the top electrode, forming a via hole in the second dielectric layer to expose the top electrode, and forming a top electrode via in the via hole.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: A detachable atomizing device and a container thereof are provided. The container is detachably assembled to an atomizing assembly. The container includes a cup and a flexible film. The cup has an opening arranged at an end thereof, the flexible film covers the opening of the cup, and the flexible film has a tension region and an outer ring-shaped region that surrounds the tension region. The tension region has a plurality of atomizing holes having an average diameter within a range of 1 ?m to 20 ?m, and the outer ring-shaped region is attached to the cup. When the cup is assembled to the atomizing assembly, a tension value of the tension region of the flexible film is increased from an initial tension value to an atomizing tension value by being pressed from the atomizing assembly, and the atomizing holes of the tension region are configured to allow liquid to pass there-through and to be formed as aerosol mist having an average atomized particle diameter less than a predetermined value.

Abstract: The present disclosure describes a method utilizing an ion beam etch process, instead of a RIE etch process, to form magnetic tunnel junction (MTJ) structures. For example, the method includes forming MTJ structure layers on an interconnect layer, where the interconnect layer includes a first area and a second area. The method further includes depositing a mask layer over the MTJ structure layers in the first area and forming masking structures over the MTJ structure layers in the second area. The method also includes etching with an ion beam etch process, the MTJ structure layers between the masking structures to form MTJ structures over vias in the second area of the interconnect layer; and removing, with the ion beam etch process, the mask layer, the top electrode, the MTJ stack, and a portion of the bottom electrode in the first area of the interconnect layer.

Abstract: A semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ILD) layer over the conductive feature, and a metal-containing etch-stop layer (ESL) disposed on the via, where the metal-containing ESL includes a first metal and is resistant to etching by a fluorine-containing etchant. The semiconductor structure further includes a conductive line disposed over the metal-containing ESL, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. Furthermore, the semiconductor structure includes a second ILD layer disposed over the first ILD layer.

Abstract: Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: A device for measuring brain oxygen level of a subject, including a probe (210) and a detecting means (220), which are respectively coupled to a processor (230). According to the example, the probe (210) includes three light sources (215a, 215b, 215c) that simultaneously emit the first, second, and third NIR wavelengths across the brain of the subject. The first NIR wavelength is the isosbestic wavelength for oxy-hemoglobin (HbO2) and deoxy-hemoglobin (Hb), the second NIR wavelength is shorter than the first NIR wavelength, and the third NIR wavelength is longer than the first NIR wavelength. The detecting means (220) includes a first, second and third detectors (221, 222, 223) for respectively detecting the NIR intensities of the first, second and third NIR wavelengths traveled across the brain. The processor (230) is configured to determine blood oxygen level based on the measured NIR intensities of the first, second and third NIR wavelengths by use of build-in algorithm derived from Beer-Lambert Law.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises receiving a structure including a substrate and a first hard mask over the substrate, the first hard mask having at least two separate portions; forming spacers along sidewalls of the at least two portions of the first hard mask with a space between the spacers; forming a second hard mask in the space; forming a first cut in the at least two portions of the first hard mask; forming a second cut in the second hard mask; and depositing a cut hard mask in the first cut and the second cut.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a metal feature in a first dielectric layer, an etch stop layer (ESL) over the metal feature, a second dielectric layer over the ESL, a third dielectric layer over the second dielectric layer, a patterned hard mask having a trench. The method further includes forming a via opening through the trench in the patterned hard mask, the second dielectric layer, the third dielectric layer, and the ESL to expose the metal feature, depositing a metal layer in the trench and the via opening to form a metal line and a metal contact via, respectively, and over the workpiece, removing the patterned hard mask between the metal line and the metal contact via, and depositing a fourth dielectric layer between the metal line and the metal contact via.

Abstract: A circuit device having an interlayer dielectric with pillar-type air gaps and a method of forming the circuit device are disclosed. In an exemplary embodiment, the method comprises receiving a substrate and depositing a first layer over the substrate. A copolymer layer that includes a first constituent polymer and a second constituent polymer is formed over the first layer. The first constituent polymer is selectively removed from the copolymer layer. A first region of the first layer corresponding to the selectively removed first constituent polymer is etched. The etching leaves a second region of the first layer underlying the second constituent polymer unetched. A metallization process is performed on the etched substrate, and the first layer is removed from the second region to form an air gap. The method may further comprise depositing a dielectric material within the etched first region.

Abstract: A semiconductor structure includes an integrated circuit, a first dielectric layer over the integrated circuit, an etch stop layer over the first dielectric layer, a barrier layer over the etch stop layer, a conductive layer over the barrier layer, and a void region vertically extending through the conductive layer, the barrier layer, and the etch stop layer. The void region has an upper portion, a middle portion below the upper portion, and a lower portion below the middle portion, the middle portion. The middle portion is narrower than the upper portion and the lower portion.

Abstract: In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second) gate electrode layer and first (second) sidewall spacers disposed on both side faces of the first (second) gate electrode layer. The first and second gate electrode layers are recessed and the first and second sidewall spacers are recessed, thereby forming a first space and a second space over the recessed first and second gate electrode layers and first and second sidewall spacers, respectively. First and second protective layers are formed in the first and second spaces, respectively. First and second etch-stop layers are formed on the first and second protective layers, respectively. A first depth of the first space above the first sidewall spacers is different from a second depth of the first space above the first gate electrode layer.

Abstract: Methods of fabricating MRAM devices are provided. The method includes forming an etch stop layer over a substrate, and depositing a bottom electrode layer on the etch stop layer. The method also includes patterning the bottom electrode layer to form a bottom electrode. The method further includes depositing a magnetic tunnel junction (MTJ) layer on the bottom electrode, and depositing a top electrode layer on the MTJ layer. In addition, the method includes patterning the top electrode layer to form a top electrode, and patterning the MTJ layer to form an MTJ structure.

Abstract: A method of fabricating an MRAM device includes forming a bottom electrode over a semiconductor substrate, forming a magnetic tunnel junction (MTJ) structure on the bottom electrode, and forming a top electrode on the MTJ structure. The method also includes forming spacers on sidewalls of the top electrode and the MTJ structure, and depositing a first dielectric layer to surround the spacers. The method further includes selectively depositing a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the method includes depositing a second dielectric layer on the patterned etch stop layer and the top electrode, forming a via hole in the second dielectric layer to expose the top electrode, and forming a top electrode via in the via hole.

Abstract: An integrated circuit includes a substrate, a dielectric layer, an etch stop layer, a bottom electrode, a resistance switching element, and a top electrode. The dielectric layer is over the substrate. The etch stop layer is over the dielectric layer, in which the dielectric layer has a first portion directly under the etch stop layer. The bottom electrode penetrates through the etch stop layer and the dielectric layer, in which the dielectric layer has a second portion directly under the bottom electrode, and a top of the first portion of the dielectric layer is lower than a top of the second portion of the dielectric layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element.

Abstract: A method of forming a semiconductor device includes providing a precursor. The precursor includes a substrate; a gate stack over the substrate; a first dielectric layer over the gate stack; a gate spacer on sidewalls of the gate stack and on sidewalls of the first dielectric layer; and source and drain (S/D) contacts on opposing sides of the gate stack. The method further includes recessing the gate spacer to at least partially expose the sidewalls of the first dielectric layer but not to expose the sidewalls of the gate stack. The method further includes forming a spacer protection layer over the gate spacer, the first dielectric layer, and the S/D contacts.

Abstract: An interconnect structure includes a first dielectric layer, an etch stop layer, a conductive via, a conductive line, an intermediate conductive layer, a conductive pillar, and a second dielectric layer. The etch stop layer is over the first dielectric layer. The conductive via is in the first dielectric layer and the etch stop layer. The conductive line is over the conductive via. The intermediate conductive layer is over the conductive line. The conductive pillar is over the intermediate conductive layer. The second dielectric layer surrounds the conductive line, the intermediate conductive layer, and the conductive pillar, and a bottom of the second dielectric layer is lower than a top of the conductive line, and a top of the second dielectric layer is higher than the top of the conductive line.

Abstract: A method of forming an interconnect structure for an integrated circuit device is provided. The method includes forming a wiring layer having a metal line, and forming a patterned disposable material layer over the wiring layer and having an opening aligned with the metal line. The method also includes depositing a first dielectric film in the opening and in contact with the metal line, and removing the patterned disposable material layer to leave the first dielectric film. The method further includes depositing a second dielectric film over the first dielectric film, and etching the second dielectric film to form a trench above the first dielectric film. In addition, the method includes removing a portion of the first dielectric film to form a via hole under the trench, and depositing a conductive material in the trench and the via hole.