Abstract: A package structure including a first semiconductor die, a second semiconductor die, a molding compound, a bridge structure, through insulator vias, an insulating encapsulant, conductive bumps, a redistribution layer and seed layers is provided. The molding compound encapsulates the first and second semiconductor die. The bridge structure is disposed on the molding compound and electrically connects the first semiconductor die with the second semiconductor die. The insulating encapsulant encapsulates the bridge structure and the through insulator vias. The conductive bumps are electrically connecting the first and second semiconductor dies to the bridge structure and the through insulator vias. The redistribution layer is disposed on the insulating encapsulant and over the bridge structure. The seed layers are respectively disposed in between the through insulator vias and the redistribution layer.

Abstract: A photonic assembly includes: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die including waveguides and photonic devices therein, and the EIC die including semiconductor devices therein; and an optical connector unit including a first connector-side mirror reflector and a first transition edge coupler, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler.

Abstract: A photonic assembly includes: a composite die including a photonic integrated circuits (PIC) die and an electronic integrated circuits (EIC) die, the PIC die including waveguides and photonic devices therein, and the EIC die including semiconductor devices therein; an optical connector unit including a first connector-side mirror reflector and a first transition edge coupler and attached to a top surface of the composite die, wherein the first connector-side mirror reflector is configured to change a beam direction between a vertically-extending beam path through the composite die and a horizontally-extending beam path through the first transition edge coupler; and a fiber array units assembly attached to a sidewall of the optical connector unit.

Abstract: A semiconductor device includes a circuit substrate, a semiconductor package, and a package frame. The semiconductor package is disposed on the circuit substrate. The package frame is disposed over the circuit substrate. The package frame encircles the semiconductor package. The semiconductor package has a first surface facing the circuit substrate and a second surface opposite to the first surface. The package frame leaves exposed at least a portion of the second surface of the semiconductor package. The package frame forms a cavity, which cavity encircles the semiconductor package.

Abstract: A computer-assisted needle insertion system and a computer-assisted needle insertion method are provided. The computer-assisted needle insertion method includes: obtaining a first machine learning (ML) model and a second ML model; obtaining a computed tomography (CT) image and a needle insertion path, generating a suggested needle insertion path according to the first ML model, the CT image, and the needle insertion path, and instructing a needle to approach a needle insertion point on a skin of a target, wherein the needle insertion point is located on the suggested needle insertion path; obtaining a breath signal of the target, and estimating whether a future breath state of the target is normal according to the second ML model and the breath signal; and outputting a suggested needle insertion period according to the breath signal in response to determining that the future breath state is normal.

Abstract: A semiconductor device includes a substrate, a heat dissipation dielectric layer, a conductive interconnect structure, and a blocking dielectric layer. The heat dissipation dielectric layer is disposed on the substrate and has a thermal conductivity greater than 10 W/mK. The conductive interconnect structure is disposed in the heat dissipation dielectric layer. The blocking dielectric layer is disposed in the heat dissipation dielectric layer to isolate the conductive interconnect structure from the heat dissipation dielectric layer.

Abstract: A wearable device includes a host, a side head strap module, and an upper head strap module. The host has a sliding rail. The side head strap module is connected to the host. The upper head strap module includes a sliding base, a front buckle, and an upper head strap. The sliding base is detachably coupled to the sliding rail and slides along the sliding rail. The sliding rail has a first engaging part. The sliding base has a second engaging part. An engagement between the first engaging part and the second engaging part temporarily fixes the sliding base to the sliding rail. The front buckle is pivotally connected to the sliding base. The upper head strap is connected between the side head strap module and the front buckle. In addition, an upper head strap module applied to the wearable device is also proposed.

Abstract: A method for establishing a disease prediction model is provided. The method includes the steps of extracting feature values for multiple microbiota features from microbiota data of each of a plurality of samples, selecting a portion of the extracted microbiota features as selected features, and training a disease prediction model. Each piece of training data used in training the disease prediction model includes (i) disease data for each of the samples and (ii) the feature values of the selected features for the sample. The microbiota features include species-level features, microbiota interaction features, and community-level features.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first device die; a second device die, stacked on the first device die; and first electrical connectors and second electrical connectors, disposed in between the first and second device dies. A first pitch between the first electrical connectors is greater than a second pitch between the second electrical connectors. The first and second electrical connectors respectively comprise a solder joint and first metallic layers lying at opposite sides of the solder joint and formed of a first metallic material. Each of the second electrical connectors further comprises at least one second metallic layer formed of a second metallic material.

Abstract: An information processing method includes, when determining that a target node in a to-be-processed chassis is used as a management node of the to-be-processed chassis, obtaining a virtual address and assigning the virtual address to the target node, notifying a subnet corresponding to the to-be-processed chassis with the virtual address, and performing communication with a target programmable module of the to-be-processed chassis through the target node and management on data of the to-be-processed chassis. The virtual address is used to inform that the target node is the management node.

Abstract: A method for forming a semiconductor device structure includes forming a plurality of fin structures from a substrate, each fin structure having first and second semiconductor layers alternatingly stacked, forming an isolation region around the fin structures, forming a first liner layer on exposed surfaces of the fin structures and the isolation region, forming a second liner layer on the first liner layer, selectively removing a portion of the second liner layer so that the second liner layer remains over sidewall of each fin structure, forming an insulating layer on the first and second liner layers, removing the second liner layer, forming a sacrificial gate structure over a portion of the fin structure and the insulating layer, removing a portion of the fin structure not covered by the sacrificial gate structure, forming a source/drain feature such that a gap is formed around and separate the source/drain feature from the insulating layer, and forming a sealing material on the source/drain feature and th

Abstract: A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, an encapsulant, a protection layer and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The encapsulant is disposed over the interposer and laterally encapsulating the at least one semiconductor die. The connectors are disposed on the second surface of the interposer and electrically connected with the at least one semiconductor die through the interposer. The protection layer is disposed on the second surface of the interposer and surrounding the connectors. The sidewalls of the interposer include slanted sidewalls connected to the second surface, and the protection layer is in contact with the slant sidewalls of the interposer.

Abstract: A system and method for reducing thermal transfer in a dual ampoule system. The dual ampoule system includes a first ampoule, a second ampoule, and a planar heat shield. The planar heat shield is positioned between the first ampoule and the second ampoule, where the planar heat shield is configured to resist thermal transfer between the first ampoule and the second ampoule.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Abstract: A shift control method in manufacture of semiconductor device includes: calculating a difference of a relative position between a conductive connector of a semiconductor die and a conductive pad of the semiconductor die relative to a reference mark on the semiconductor die; placing the semiconductor die over a carrier, wherein the difference is compensated when placing the semiconductor die over the carrier; and forming a lithographic pattern on the conductive connector of the semiconductor die.

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

Abstract: An electronic device, including a metal back cover, a ground radiator, a third radiator, and a metal frame including a first cutting opening, a second cutting opening, a first radiator located between the first cutting opening and the second cutting opening, and a second radiator located beside the second cutting opening and separated from the first radiator by the second cutting opening, is provided. An end of a first slot formed between the metal back cover and a first part of the first radiator is communicated with the first cutting opening, and a second slot formed between the metal back cover and a second part of the first radiator and between the metal back cover and the second radiator is communicated with the second cutting opening. The ground radiator connects the metal back cover and the first radiator and separates the first slot from the second slot.