Abstract: An apparatus and method are provided. The apparatus includes a phase locked loop (PLL) configured to generate a reference signal; a sub-sampling PLL (SS-PLL) connected to the PLL and configured to sub-sample the reference signal; and a first pre-charge circuit connected to the SS-PLL and configured to allow an output voltage of the SS-PLL to transition to an operating voltage to indicate that a difference between two voltage inputs is zero on average.

Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

Abstract: An apparatus for providing fast-settling quadrature detection and correction includes: a quadrature correction circuit that receives four quadrature clock signals; a quadrature detector that selects two clock signals among the four quadrature clock signals; and a phase digitizer that generates a digital code indicating a phase difference between the two clock signals. The quadrature correction circuit adjusts a phase between the two clock signals using the digital code.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.

Abstract: A synchronized in-phase/quadrature phase (I/Q) detection circuit and a method of the same are provided. The synchronized I/Q detection circuit includes a first logic circuit; a first filter; a first reset and sampling circuit; a first multiplexer; a second logic circuit; a second filter; a second reset and sampling circuit; a signal generator; and a comparator.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.

Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.

Abstract: A system and method for fast converging reference clock duty cycle correction for a digital to time converter (DTC) based analog fractional-N phase-locked loop (PLL) are herein disclosed. According to one embodiment, an electronic circuit includes a clock doubler, a comparator that outputs a value representing a difference between a voltage at a voltage-to-current (Gm) circuit and a reference voltage that is adjusted to compensate for an offset of the comparator, and a duty cycle calibration circuit that receives the value output from the comparator and adjusts a duty cycle of the PLL by extracting an error from the value output from the comparator and delaying a clock edge of the duty cycle according to the extracted error.

Abstract: A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

Abstract: An apparatus and a method are provided. The apparatus includes an analog-to-digital converter (ADC) driver; and an ADC that is electrically coupled to the ADC driver. The method includes setting, by an analog-to-digital converter (ADC) driver, a desired common-mode control value based on the held voltage; and setting, by the ADC driver, a desired gain control value based on the held voltage.

Abstract: A system and method for calibrating a duration of a pulse or a delay. A reference clock signal includes a sequence of reference pulses, and controls a switch in a first charge pump that is configured to charge a first capacitor. Each of a sequence of test pulses controls a switch in a second charge pump that is configured to charge a second capacitor. At the end of each charging cycle, the respective capacitor voltages are compared and the duration of the test pulses is adjusted, by a feedback circuit, in a direction tending to make the capacitor voltages equal. When the capacitor voltages are equal, the ratio of the lengths of the reference pulses and test pulses equals the ratio of the capacitances, if the charge pumps deliver the same current when switched on.

Abstract: An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.

Abstract: An apparatus and a method. The apparatus includes a counter array; a ring oscillator that is electrically coupled to the counter array, where the counter array counts a number of cycles in the ring oscillator; an analog-to-digital converter (ADC) driver that is electrically coupled to the ring oscillator; and an ADC that is electrically coupled to the ADC driver, where an output of the ADC is electrically coupled to the ring oscillator.

Abstract: An apparatus and a method. The apparatus includes a delay processor, a coarse converter and node selector connected to the delay processor and configured to select a first voltage V1 and a second voltage V2 of opposite polarities of adjacent stages of the delay processor, a fine converter connected to the coarse converter and node selector and configured to determine a zero-crossing time associated with the first voltage V1 and the second voltage V2; and an encoder connected to the coarse converter and the fine converter and configured to receive and encode the first voltage V1, the second voltage V2 and the zero-crossing time, wherein V1 is a first negative voltage before the zero-crossing time, and V2 is a first positive voltage after the zero-crossing time.

Abstract: Methods, apparatuses, and systems for providing a variable output using an array of cells are discussed. In the fine tuning bank of an apparatus, control is implemented by selecting a boundary cell from the array of cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.

Abstract: Methods, apparatuses, and systems for providing a variable output using an array of cells are discussed. In the fine tuning bank of an apparatus, control is implemented by selecting a boundary cell from the array of cells and having every cell before the boundary cell in a circuit path be grounded and having the boundary cell and every cell after the boundary cell in the circuit path be connected to a voltage source. The circuit path may be the one formed by using thermometer coding in the fine tuning bank.

Abstract: A system using temperature tracking for a controlled oscillator (CO) is provided. The system includes at least one coarse tuning capacitor circuit including a plurality of selectable coarse tuning capacitors operable in at least three modes of operation, thereby allowing switching between each coarse capacitor of the plurality of selectable coarse capacitors when a selected coarse tuning capacitor has reached one of its high tuning range and low tuning range.