Patents by Inventor Chih-Wen (Albert) Yao
Chih-Wen (Albert) Yao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250119631Abstract: An imaging lens module has an image surface and includes an optical lens assembly, a plurality of monomer structures and a cover member. The optical lens assembly is disposed on an object side of the image surface and defines an optical axis. The optical lens assembly includes a light-blocking element, which includes a light-blocking portion. The light-blocking portion is disposed closer to the optical axis than a portion of the light-blocking element other than the light-blocking portion thereto. The monomer structures are disposed on the object side of the image surface, and each of the monomer structures is extended along a direction parallel to the optical axis. The cover member is disposed on an object side of the optical lens assembly, and the optical axis passes through the cover member. The monomer structures are disposed on the light-blocking portion of the light-blocking element.Type: ApplicationFiled: September 26, 2024Publication date: April 10, 2025Inventors: Chih-Wen HSU, Heng-Yi SU
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Patent number: 12272592Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.Type: GrantFiled: May 15, 2024Date of Patent: April 8, 2025Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
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Patent number: 12273389Abstract: A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.Type: GrantFiled: March 22, 2022Date of Patent: April 8, 2025Assignee: International Business Machines CorporationInventors: Jeff Hsueh-Chang Kuo, June-Ray Lin, Ying-Chen Yu, Chih-Wen Su
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Patent number: 12274070Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.Type: GrantFiled: July 4, 2022Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Ting Lin, Wei-Chih Wen, Kai-Wen Cheng, Wu-Wei Tsai, Yu-Ming Hsiang, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 12274077Abstract: A method of forming a semiconductor memory device includes: forming a stack structure on a substrate, the stack structure including a plurality of dielectric layers and a plurality of sacrificial layers alternatingly stacked in a Z direction substantially perpendicular to the substrate; forming a plurality of source/drain trenches in the stack structure; conformally forming a barrier layer in the source/drain trenches, and then filling the source/drain trenches with a plurality of sacrificial segments; forming a protection layer over the stack structure to cover the barrier layer and the sacrificial segments; removing the sacrificial layers of the stack structure to form a plurality of spaces among the dielectric layers; forming a plurality of conductive layers in the spaces; sequentially removing the protection layer, the sacrificial segments and the barrier layer; and forming a plurality of memory structures in the source/drain trenches.Type: GrantFiled: May 26, 2022Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Chih Wen, Yu-Wei Jiang, Han-Jong Chia
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Publication number: 20250110307Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Patent number: 12265208Abstract: An optical device includes a range finding module. The range finding module includes a first light condenser unit, a light emitting unit and a light receiving unit. The first light condenser unit defines an optical axis and a hole disposed along the optical axis. The first light condenser unit, the light emitting unit and the light receiving unit are sequentially arranged along the optical axis. The light is emitted by the light emitting unit, passes through the hole, reaches an object, is reflected by the object, is converged by the first light condenser unit and is received by the light receiving unit to generate an electrical signal.Type: GrantFiled: May 9, 2022Date of Patent: April 1, 2025Assignees: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.Inventors: Kung-Hsin Teng, Yan-Rong Fan, Hsien-Chi Lin, Zhi-You Dai, Chun-Chou Lin, Chih-Wen Wang, Jia-Zhong Hsu
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Patent number: 12261610Abstract: A frequency locked loop circuit, comprising an operational circuit, a first impedance circuit, a second impedance circuit, a switching circuit and a frequency generation circuit. The operational circuit is configured to output an operational signal according to a voltage difference between a positive terminal and a negative terminal. The switching circuit is configured to periodically conduct the negative terminal to one of the first impedance node and the second impedance node, and periodically conduct the positive terminal to the other one of the first impedance node and the second impedance node. The frequency generation circuit is configured to periodically sample the operational signal to generate a sample signal to generate a clock signal. An operational frequency of the operational signal is an integer multiple of a sampling frequency of the frequency generation circuit.Type: GrantFiled: October 29, 2023Date of Patent: March 25, 2025Assignee: NOVATEK Microelectronics Corp.Inventors: Chin-Tung Chan, Yan-Ting Wang, Ren-Hong Luo, Chih-Wen Chen, Hao-Che Hsu, Li-Wei Lin
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Patent number: 12249108Abstract: A 3D image sensing device includes a first camera lens, a second camera lens and a light source. A 3D image processing method for the 3D image sensing device includes the following steps. Firstly, a target is photographed by the first camera lens and the second camera lens, and the obtained images are processed in a stereo vision mode. Consequently, a first depth map is obtained. After the light source emits plural feature points to the target, the target is photographed by the first camera lens and the second camera lens, and the obtained images are processed in an active stereo vision mode. Consequently, a second depth map is obtained. The first depth map and the second depth map are synthesized as a synthesized depth map according to a synthetization strategy.Type: GrantFiled: January 17, 2023Date of Patent: March 11, 2025Assignee: PRIMAX ELECTRONICS LTD.Inventors: Hsiu-Wen Wang, Chih-Wen Lin
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Publication number: 20250081470Abstract: In a method of manufacturing a semiconductor device, a magnetic random access memory (MRAM) cell structure is formed. The MRAM cell structure includes a bottom electrode, a magnetic tunnel junction (MTJ) stack and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. An interlayer dielectric (ILD) layer is formed. A contact opening in the ILD layer is formed, thereby exposing the second insulating cover layer. A part of the second insulating cover layer and a part of the first insulating cover layer are removed, thereby exposing the top electrode. A conductive layer is formed in the opening contacting the top electrode.Type: ApplicationFiled: November 19, 2024Publication date: March 6, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-Hsien WEI, Chung-Te LIN, Han-Ting TSAI, Tai-Yen PENG, Yu-Teng DAI, Chien-Min LEE, Sheng-Chih LAI, Wei-Chih WEN
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Publication number: 20250079684Abstract: An antenna module and a related network communication device are provided in this disclosure. A network communication device includes a circuit board, a network communication chip, an antenna, a signal line, and an antenna bracket. The network communication chip is disposed on the circuit board. The antenna bracket has a first antenna slot, a circuit board slot, a circuit board hook and an opposite supporting part. The first antenna slot is configured to carry the antenna. The circuit board hook and the opposite supporting part are respectively located on opposing first surface and second surface of the circuit board. The circuit board slot is located between the circuit board hook and the opposite supporting part to accommodate the circuit board. The circuit board hook is buckled to a first buckle hole of the circuit board.Type: ApplicationFiled: August 2, 2024Publication date: March 6, 2025Applicant: Sercomm CorporationInventors: Chih Wen Tseng, Chia Chun Sun
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Publication number: 20250066622Abstract: The present invention provides a method for preparing conductor material with large surface area, which comprises steps of: forming a block layer on the outer surface of a support precursor (for example, a conductive nanometer fiber) for producing a mixed precursor; rolling the mixed precursor to crack a portion of the outer surface of the block layer for producing a plurality of crack-gaps and exposing a portion of the outer surface of the support precursor from the plurality of crack-gaps; and adding a conductor material to the mixed precursor so that the conductor material contacts and is connected electrically to the support precursor via the plurality of crack-gaps for producing a conductor material with large surface area.Type: ApplicationFiled: November 17, 2023Publication date: February 27, 2025Inventors: Ting-Keng Lin, Chih-Wen Wu
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Publication number: 20250072071Abstract: A transistor structure includes a substrate, a first well region, a second well region, a gate structure, a drift region, a first doped region, a second doped region, and a first isolation structure. The first well region and the second well region are located in the substrate and adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The first doped region is located in the first well region. The second doped region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doped region. The first well region has a first portion lower than a bottom surface of the drift region. The second well region has a second portion lower than the bottom surface of the drift region.Type: ApplicationFiled: September 15, 2023Publication date: February 27, 2025Applicant: United Microelectronics Corp.Inventors: Chih Wen Huang, Shih An Huang
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Publication number: 20250062753Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.Type: ApplicationFiled: June 20, 2024Publication date: February 20, 2025Applicant: DigWise Technology Corporation, LTDInventors: Hung-Lin Wu, Chih-Wen Yang, Yu-Chen Lo
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Patent number: 12219880Abstract: A memory device includes a bottom electrode contact, a magnetic tunnel junction pattern, a protection insulating layer, a first capping layer, an interlayer insulating layer, and a second capping layer. The magnetic tunnel junction pattern is over the bottom electrode contact. The protection insulating layer surrounds the magnetic tunnel junction pattern. The first capping layer surrounds the protection insulating layer. The interlayer insulating layer surrounds the first capping layer. The second capping layer is over the first capping layer and the interlayer insulating layer.Type: GrantFiled: March 4, 2024Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Sheng-Chih Lai, Han-Ting Tsai, Chung-Te Lin
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Patent number: 12218301Abstract: A manufacturing method of an electronic device includes: forming a conductive material layer on a substrate, the conductive material layer continuously extends from a first surface of the substrate to a second surface while passing through a side surface, wherein the side surface connects the first surface and the second surface, forming a first protection layer on the conductive material layer and patterning the conductive material layer by using the first protection layer as a mask to form an edge wire, wherein the edge wire is retracted relative to the first protection layer and forms an undercut structure, and forming a second protection layer on the substrate, wherein the second protection layer fills the undercut structure.Type: GrantFiled: January 16, 2024Date of Patent: February 4, 2025Assignee: AUO CorporationInventors: Chih-Wen Lu, Hao-An Chuang, Chun-Yueh Hou
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Patent number: 12204163Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: February 5, 2024Date of Patent: January 21, 2025Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 12189234Abstract: A multilayer light diffuser plate and a method for manufacturing the same are disclosed. The multilayer light diffusion plate comprises a main layer and a partially-transmissive and partially-reflective layer located under the main layer. The top surface of the main layer is the light-emitting surface, and the light-incident surface is the bottom surface of the partially-transmissive and partially-reflective layer. The partially-transmissive and partially-reflective layer comprises a plurality of first base material layers and a plurality of second base material layers stacked alternately. The materials of the first and second base material layers have different refractive indices. The partially-transmissive and partially-reflective layer formed by alternately stacking the first and second base material layers with different refractive indices is arranged on the light-incident surface of the light diffuser plate by means of extrusion, which is simpler and less expensive to manufacture.Type: GrantFiled: October 7, 2023Date of Patent: January 7, 2025Assignee: ENTIRE TECHNOLOGY CO., LTD.Inventors: Chih Wen Yang, Yu Wei Chang, Mao Hsing Lin
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Patent number: 12189149Abstract: A light blocking sheet having a central axis includes a central hole and a plurality of inner extended portions. The central axis passes through the central hole, which is enclosed by a hole inner surface. The hole inner surface has a first corresponding circle and a second corresponding circle, wherein a diameter of the first corresponding circle is greater than a diameter of the second corresponding circle. The inner extended portions are adjacent to and surround the central hole, wherein each of the inner extended portions is extended and tapered from the first corresponding circle towards the second corresponding circle and includes an inner surface, and the inner surface includes a line pair. The line pair includes two line sections, wherein one end of one line section thereof and one end of the other line section thereof are towards the second corresponding circle and approach to each other.Type: GrantFiled: June 19, 2023Date of Patent: January 7, 2025Assignee: LARGAN PRECISION CO., LTD.Inventors: Ming-Ta Chou, Ming-Shun Chang, Chih-Wen Hsu
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Patent number: D1063925Type: GrantFiled: January 21, 2021Date of Patent: February 25, 2025Assignee: COMPAL ELECTRONICS, INC.Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee