Patents by Inventor Chih-Wen Hsiao

Chih-Wen Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10432200
    Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors; a plurality of second anchors; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 1, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Shao-Cheng Hsiao
  • Publication number: 20190295748
    Abstract: A method for manufacturing a shunt resistor is described. In this method, a first electrode plate and a second electrode plate are provided. The first electrode plate includes a first carrying portion having a first hole. The second electrode plate includes a second carrying portion having a second hole. A resistor plate is placed between the first and second electrode plates. The resistor plate has a first through hole and a second through hole respectively on the first hole and the second hole. A first rivet is pressed into the first through hole and the first hole. A second rivet is pressed into the second through hole and the second hole. Current is applied to the first rivet and the second rivet to weld the first rivet, the first electrode plate and the resistor plate, and to weld the second rivet, the second electrode plate and the resistor plate.
    Type: Application
    Filed: April 26, 2018
    Publication date: September 26, 2019
    Inventors: Shen-Li HSIAO, Kuang-Cheng LIN, Hwan-Wen LEE, Chih-Lung CHEN
  • Publication number: 20190287701
    Abstract: In a method for manufacturing a shunt resistor, a resistor plate with a first side surface and a second side surface opposite to each other is provided. A first electrode plate and a second electrode plate are respectively pressed onto the first side surface and the second side surface, thereby forming a first connection surface between the first electrode plate and the resistor plate, and a second connection surface between the second electrode plate and the resistor plate. A first conductive module is placed on opposite ends of the first connection surface, and a second conductive module is placed on opposite ends of the second connection surface. Current is applied to the first and second connection surfaces via the first and second conductive modules respectively to weld the first electrode plate and the resistor plate, and to weld the second electrode plate and the resistor plate.
    Type: Application
    Filed: April 26, 2018
    Publication date: September 19, 2019
    Inventors: Shen-Li HSIAO, Kuang-Cheng LIN, Hwan-Wen LEE, Chih-Lung CHEN
  • Patent number: 10361181
    Abstract: A semiconductor package includes a package substrate. A redistribution structure is bonded to the package substrate. A bottommost surface of the redistribution structure is lower than a topmost surface of the package substrate. A conductive connector electrically couples the redistribution structure to the package substrate. The conductive connector physically contacts a sidewall of the redistribution structure. A first integrated circuit die is bonded to the redistribution structure through first bonding structures and is bonded to the package substrate through second bonding structures. The first bonding structures and the second bonding structures have different sizes.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: July 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 10354931
    Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Patent number: 10348203
    Abstract: A DC-to-DC controller, a DC-to-DC power converter and a control method thereof are provided. The controller is coupled to an upper-bridge switch and a lower-bridge switch and includes a time generation unit providing a time signal, a voltage identification (VID) change determining circuit and a time control circuit. The VID change determining circuit provides a determination signal in response to a VID signal. The time control circuit provides a control signal according to the time signal and the determination signal. When the VID signal changes from high to low, the time control circuit turns off the upper-bridge switch for a first preset time according to the determination signal and the time signal, and during the first preset time, the time control circuit controls the lower-bridge switch to be turned on for a second preset time multiple times, and to be turned off for a third preset time multiple times.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 9, 2019
    Assignee: uPI Semiconductor Corp.
    Inventors: Chih-Wen Hsiao, Chih-Lien Chang
  • Publication number: 20190203383
    Abstract: A conductive elastic fiber and a method for fabricating the conductive elastic fiber are provided. The method for fabricating the conductive elastic fiber includes following steps. A first solution is provided, where the first solution includes an elastic polymer dissolved in a first solvent, wherein the weight ratio of the elastic polymer to the first solvent is from 5:95 to 20:80. A second solution is provided, where the second solution includes a conductive material dispersed in a second solvent, wherein the weight ratio of the conductive material to the second solvent is from 5:95 to 20:80. Next, a wet spinning process employing the first solution and the second solution is performed to obtain the conductive elastic fiber.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chung-Yang CHUANG, Kai-Jen HSIAO, Chih-Lung CHEN, Jing-Wen TANG
  • Publication number: 20180337598
    Abstract: A DC-to-DC controller, a DC-to-DC power converter and a control method thereof are provided. The controller is coupled to an upper-bridge switch and a lower-bridge switch and includes a time generation unit providing a time signal, a voltage identification (VID) change determining circuit and a time control circuit. The VID change determining circuit provides a determination signal in response to a VID signal. The time control circuit provides a control signal according to the time signal and the determination signal. When the VID signal changes from high to low, the time control circuit turns off the upper-bridge switch for a first preset time according to the determination signal and the time signal, and during the first preset time, the time control circuit controls the lower-bridge switch to be turned on for a second preset time multiple times, and to be turned off for a third preset time multiple times.
    Type: Application
    Filed: February 5, 2018
    Publication date: November 22, 2018
    Applicant: uPI Semiconductor Corp.
    Inventors: Chih-Wen Hsiao, Chih-Lien Chang
  • Publication number: 20180331619
    Abstract: A DC-to-DC controller and a control method thereof are provided. The DC-to-DC controller couples to an output stage, and the output stage provides an output voltage and includes an upper bridge switch and a lower bridge switch. The DC-to-DC controller includes a time signal generating unit and a time signal control circuit. The time signal control circuit couples to the time signal generating unit and receives a preset voltage and the output voltage. During a soft start period, if the output voltage is lower than the preset voltage, after the upper bridge switch is turned off and before the upper bridge switch is turned on again, the time signal control circuit turns off the upper bridge switch and the lower bridge switch for a first preset time and turns on the lower bridge switch for a second preset time.
    Type: Application
    Filed: February 5, 2018
    Publication date: November 15, 2018
    Applicant: uPI Semiconductor Corp.
    Inventors: Chih-Wen Hsiao, Chih-Lien Chang
  • Patent number: 10103727
    Abstract: A power switch circuit includes a first input voltage, a first switch element, a switcher, a first bootstrap capacitor, and a second bootstrap capacitor. The first switch element includes a first control end, a first input end, and a first output end. The first input end is coupled to the first input voltage. The first output end provides an output voltage. The switcher is coupled to the first switch element. The first bootstrap capacitor is coupled to the switcher and provides a first driving voltage. The second bootstrap capacitor is coupled to the switcher and provides a second driving voltage. The first bootstrap capacitor and the second bootstrap capacitor alternately supply the first driving voltage or the second driving voltage to the first control end through an operation of the switcher.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: October 16, 2018
    Assignee: uPI Semiconductor Corp.
    Inventors: Chih-Wen Hsiao, Wen-Chieh Tsai
  • Patent number: 9852860
    Abstract: A method for generating a current adapted to a parameter setting circuit is provided. The parameter setting circuit is coupled to an external setting impedor. The external setting impedor is coupled to an external voltage and outputs a first current. The method for generating the current includes the following steps. A reference voltage and an end voltage of a reference resistor are compared to get a comparison result. The end voltage is adjusted according to a comparison result. A setting parameter is obtained according to the adjusted end voltage. A setting current is generated according to a compensation current. The compensation current is related to a first current and the setting parameter. In addition, a parameter setting circuit of a power conversion apparatus is also provided.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: December 26, 2017
    Assignee: uPI Semiconductor Corp.
    Inventor: Chih-Wen Hsiao
  • Publication number: 20170133182
    Abstract: A method for generating a current adapted to a parameter setting circuit is provided. The parameter setting circuit is coupled to an external setting impedor. The external setting impedor is coupled to an external voltage and outputs a first current. The method for generating the current includes the following steps. A reference voltage and an end voltage of a reference resistor are compared to get a comparison result. The end voltage is adjusted according to a comparison result. A setting parameter is obtained according to the adjusted end voltage. A setting current is generated according to a compensation current. The compensation current is related to a first current and the setting parameter. In addition, a parameter setting circuit of a power conversion apparatus is also provided.
    Type: Application
    Filed: March 3, 2016
    Publication date: May 11, 2017
    Inventor: Chih-Wen Hsiao
  • Patent number: 9331571
    Abstract: A power converter is disclosed. The power converter includes a comparator and a timing generator. The comparator compares a first input signal with a second input signal to provide a control signal. The timing generator is coupled to the comparator. The timing generator includes a plurality of timing generating units, a logic unit, and a calculation unit. The timing generator generates a plurality of timing signals through the timing generating units and the logic unit according to the control signal, and the calculation unit forms a pulse width modulation (PWM) signal according to the timing signals. At least a part of the timing signals are overlapped.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: May 3, 2016
    Assignee: UPI SEMICONDUCTOR CORPORATION
    Inventors: Chih-Wen Hsiao, Chih-Lien Chang
  • Patent number: 9064837
    Abstract: A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: June 23, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
  • Publication number: 20140340064
    Abstract: A power converter is disclosed. The power converter includes a comparator and a timing generator. The comparator compares a first input signal with a second input signal to provide a control signal. The timing generator is coupled to the comparator. The timing generator includes a plurality of timing generating units, a logic unit, and a calculation unit. The timing generator generates a plurality of timing signals through the timing generating units and the logic unit according to the control signal, and the calculation unit forms a pulse width modulation (PWM) signal according to the timing signals. At least a part of the timing signals are overlapped.
    Type: Application
    Filed: May 8, 2014
    Publication date: November 20, 2014
    Applicant: uPI semiconductor corp.
    Inventors: Chih-Wen Hsiao, Chih-Lien Chang
  • Publication number: 20120249178
    Abstract: A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
    Type: Application
    Filed: June 11, 2012
    Publication date: October 4, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
  • Patent number: 8219340
    Abstract: A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
    Type: Grant
    Filed: May 4, 2009
    Date of Patent: July 10, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
  • Patent number: 8164113
    Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: April 24, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chih-Sheng Lin, Chih-Wen Hsiao, Keng-Li Su
  • Patent number: 7894274
    Abstract: A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: February 22, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Chih Sheng Lin, Min-Chuan Wang, Chih-Wen Hsiao, Keng-Li Su
  • Publication number: 20100237386
    Abstract: An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.
    Type: Application
    Filed: September 22, 2009
    Publication date: September 23, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Sheng Lin, Chih-Wen Hsiao, Keng-Li Su