Patents by Inventor Chih-Wen Huang

Chih-Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273031
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate; an active circuit portion including at least an active component and formed on a topside of the semiconductor device; and a radiating metal sheet formed on a backside of the semiconductor device. A hole is formed within the substrate and the hole penetrates through the substrate. The active circuit portion and the radiating metal sheet are coupled through the hole.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 5, 2019
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Publication number: 20190244917
    Abstract: A transition structure disposed in a package is disclosed. The transition structure comprises a first ground lead and a second ground lead; and a signal lead, disposed between the first ground lead and the second ground lead, wherein the first ground lead and the second ground lead have an exterior edge and an interior edge, the signal lead is coupled to a metal line formed on a printed circuit board (PCB) and a signal terminal of the die within the package; wherein an exterior gap formed between the first ground lead and the second ground lead at the exterior edge is wider than an interior gap formed between the first ground lead and the second ground lead at the interior edge.
    Type: Application
    Filed: February 7, 2018
    Publication date: August 8, 2019
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Chen-Yang Hsieh, You-Cheng Lai
  • Patent number: 10256187
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: April 9, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, You-Cheng Lai
  • Patent number: 10249170
    Abstract: A computing device includes a rail mount chassis and a processor. The rail mount chassis includes a pressure sensor. The processor monitors the pressure sensor to obtain pressure sensor data; estimates a load exerted on a rail of the rail mount chassis using the obtained pressure sensor data; makes a determination that the load exerted on the rail exceeds a load rating of the rail; and in response to the determination, notifies a user that the rail may be damaged.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 2, 2019
    Assignee: Dell Products L.P.
    Inventors: Chih-Wen Huang, Chih-Chieh Ting, Chu-Pei Tsao, Ching-Yuan Pai, Mao-Chen Wu, Tung-Sen Huang
  • Publication number: 20190088000
    Abstract: An image processing system is provided in the invention. The image processing system includes a head-mounted display and an image processing device. The image processing device includes a processor. The processor transmits helmet information corresponding to the head-mounted display to a User Mode Driver. According to the helmet information and a first framebuffer which is obtained from a Kernel Mode Driver, the User Mode Driver generates a second framebuffer. The processor directly generates display information according to the second framebuffer, and the head-mounted display receives the display information and displays a picture according to the display information.
    Type: Application
    Filed: May 16, 2018
    Publication date: March 21, 2019
    Inventors: Chih-Wen HUANG, Chao-Kuang YANG
  • Publication number: 20190088177
    Abstract: An image processing system is provided in the invention. The image processing system includes a head-mounted display and an image processing device. The image processing device includes a processor. The processor transmits setting information of the head-mounted display to a picture driver. The picture driver obtains 3D data from a User Mode Driver and generates a left-eye picture and a right-eye picture that correspond to the head-mounted display according to the setting information and the 3D data. The processor transmits the left-eye picture and the right-eye picture to the head-mounted display and the head-mounted display displays a picture according to the left-eye picture and the right-eye picture.
    Type: Application
    Filed: May 16, 2018
    Publication date: March 21, 2019
    Inventors: Chih-Wen HUANG, Chao-Kuang YANG
  • Publication number: 20180331031
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a winding structure formed on a top side the semiconductor substrate, wherein the winding structure comprises one or more metal lines winding with respect to a center of the winding structure; and a backside metal formed under a backside of the semiconductor substrate; wherein a hollow slot is formed within the backside metal, and a projection of the winding structure is within the hollow slot.
    Type: Application
    Filed: May 15, 2017
    Publication date: November 15, 2018
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, You-Cheng Lai
  • Patent number: 10037945
    Abstract: A package structure is disclosed. The package structure includes at least a lead, for delivering at least a signal; at least a routing layer, connected to the at least a lead, where at least a first hole is formed through the at least a routing layer; a die, disposed on the at least a routing layer, where at least a second hole is formed through the die, and the die generates or receives the at least a signal; and a molding cap, for covering the at least a routing layer and the die; where the at least a signal is delivered through the at least a first hole and the at least a second hole.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: July 31, 2018
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu, Fan-Hsiu Huang
  • Patent number: 9972509
    Abstract: An anti-plasma adhesive tape utilized for manufacturing a semiconductor package includes a substrate; and an adhesive layer formed on the substrate, wherein the adhesive layer is selected from a group composed of acrylic adhesive, light-curable resin and photoinitiator. The anti-plasma adhesive tape is attached to a backside of a lead frame of the semiconductor package before a plasma-cleaning process and removed from the lead frame after a molding process. After the anti-plasma adhesive tape is cured by irradiating an energy ray and removed from the lead frame, there is no residual adhesive left on a molding compound of the semiconductor package.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: May 15, 2018
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Hsiang Kuo, Chih-Wen Huang
  • Publication number: 20180108965
    Abstract: A radio frequency (RF) device includes a chip comprising a plurality of vias and at least a hot via; a signal lead and a ground lead disposed under a back side of the chip; and a signal metal sheet, a first ground metal sheet and a second ground metal sheet disposed on a top side of the chip. The signal metal sheet crosses over the first gap formed between the signal lead and the ground lead. The first ground metal sheet and the second ground metal sheet are coupled to the ground lead through the plurality of vias. The first ground metal sheet and the second ground metal sheet substantially surround the signal metal sheet.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 19, 2018
    Inventors: Chih-Wen Huang, Jui-Chieh Chiu
  • Patent number: 9922800
    Abstract: Embodiments of a method for generating ions in an ion source are provided. The method for generating ions in an ion source includes introducing a dopant gas and a diluent gas into an ion source arc chamber. The method for generating ions in an ion source further includes generating plasma in the ion source arc chamber based on the dopant gas and the diluent gas. In addition, the dopant gas includes carbon monoxide, and the diluent gas includes xenon and hydrogen.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Ming-Hui Li, Stanley Chang, Po-Yi Tseng, Chia-Cheng Liu, Chang-Chun Wu, Shen-Han Lin, Chih-Wen Huang, Ming-Hsien Wu
  • Publication number: 20180076054
    Abstract: An anti-plasma adhesive tape utilized for manufacturing a semiconductor package includes a substrate; and an adhesive layer formed on the substrate, wherein the adhesive layer is selected from a group composed of acrylic adhesive, light-curable resin and photoinitiator. The anti-plasma adhesive tape is attached to a backside of a lead frame of the semiconductor package before a plasma-cleaning process and removed from the lead frame after a molding process. After the anti-plasma adhesive tape is cured by irradiating an energy ray and removed from the lead frame, there is no residual adhesive left on a molding compound of the semiconductor package.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Inventors: Chih-Hsiang Kuo, Chih-Wen Huang
  • Patent number: 9812379
    Abstract: A semiconductor package includes a die comprising at least a via and a least a hot via; a ground lead, formed directly under a back side of the die, contacting with the back side of the die, and directly connected to the a least a hot via and the at least a via of the die; a buffer layer, formed on the die, configured to absorb a stress applied to the die and prevent the die from damage; and a molding portion, formed on the die buffer layer.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 7, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, You-Cheng Lai
  • Publication number: 20170199264
    Abstract: An EMI testing deviation correction system includes an EMI testing facility. A signal provisioning device in the EMI testing facility includes a power connector coupling coupled to a networking port. A signal generator includes a power connector that is connected to the power connector coupling, and generates and provides signals having first signal characteristics through the power connector. An ISN device is coupled to the first networking port to receive signals that are provided by the signal generator and transmitted through the signal provisioning device. A signal receiver device is coupled to the ISN device and receives signals transmitted through the signal provisioning device and the ISN device. The signals received by the signal receiver device include second signal characteristics, and the difference between the second signal characteristics and the first signal characteristics provides an indication of at least one correction for the EMI testing facility.
    Type: Application
    Filed: January 12, 2016
    Publication date: July 13, 2017
    Inventors: Chu-Pei Tsao, Mao-Chen Wu, Ching-Yuan Pai, Chih-Wen Huang, Jeng-Hua Chiu
  • Patent number: 9692370
    Abstract: A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 27, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Fan-Hsiu Huang, Chih-Wen Huang
  • Patent number: 9673152
    Abstract: A high-frequency package comprises a ground lead occupying a side of the high-frequency package; and a signal lead comprising at least a protrusion protruding from a central portion of the signal lead; wherein the ground lead and the signal lead perform as a transmission line, and the at least a protrusion forms capacitance of the transmission line.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: June 6, 2017
    Assignee: WIN Semiconductors Corp.
    Inventor: Chih-Wen Huang
  • Publication number: 20170147567
    Abstract: A file managing method for a digital apparatus includes (a) establishing a folder corresponding to a file type generated in an operational mode of the digital apparatus, and (b) storing a file according to its file type to the folder corresponding to the file type established in step (a).
    Type: Application
    Filed: September 19, 2016
    Publication date: May 25, 2017
    Inventor: Chih-Wen Huang
  • Patent number: 9660587
    Abstract: A power amplifier (PA) has been disclosed for linearity improvement. The PA comprises at least an amplifying transistor and at least an auxiliary transistor. Each amplifying transistor of the at least an amplifying transistor includes a first terminal for receiving an input signal of the PA, a second terminal for delivering an output signal of the PA, and a third terminal. Each auxiliary transistor of the at least an auxiliary transistor includes a first terminal, a second terminal coupled to the second terminal of the at least an amplifying transistor, and a third terminal electrically connected to the first terminal of the at least an amplifying transistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 23, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Fan-Hsiu Huang, Jui-Chieh Chiu, Chih-Wen Huang
  • Patent number: 9653408
    Abstract: A high-frequency package comprises a die; a plurality of leads; and a die pad; wherein a surface of the die pad is lower than top surfaces of the plurality of leads, the die is disposed on the die pad with the lower surface, such that a top surface of the die is substantially aligned with the top surfaces of the plurality of leads.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 16, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Chih-Wen Huang, Yu-Chiao Chen
  • Patent number: 9641130
    Abstract: A low noise amplifier (LNA) has been disclosed for the noise and linearity performance improvement. The LNA includes an amplifying transistor and an auxiliary transistor. The amplifying transistor includes a first terminal for receiving an input signal of the LNA, a second terminal for outputting an output signal of the LNA, and a third terminal. The auxiliary transistor has a first terminal, a second terminal coupled to the second terminal of the amplifying transistor, and a third terminal electrically connected to the first terminal of the amplifying transistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 2, 2017
    Assignee: WIN Semiconductors Corp.
    Inventors: Fan-Hsiu Huang, Jui-Chieh Chiu, Chih-Wen Huang