Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Abstract: A setup time and hold time detection system including a monitoring unit and a processing unit. The monitoring unit is configured to detect multiple setup times and multiple hold times of multiple test circuits through a source clock signal. The processing unit is configured to record multiple setup times and multiple hold times as multiple detection data. The processing unit is further configured to select a first part of the detection data as multiple first detection data to establish an estimation model. The processing unit is further configured to select a second part of the detection data as multiple second detection data, and compare the second detection data and multiple estimation results generated by the estimation model to obtain an error value of the estimation model.

Abstract: A light diffusion plate is configured to be assembled with a blue light source module having blue Mini LEDs to form a white light backlight module. The light diffusion plate is added with organic dyes with light-emission wavelength of 490-650 nm in order to convert the blue light into white light. The light diffusion plate is made by a foaming extrusion process and contains a plurality of micro-bubbles with a size of 60-400 ?m and a weight-reduction ratio of 15-25% for improving the uniformity of white light and resolving the MURA problem. The size of micro-bubbles is controlled by reducing the temperature of at the exit end of the T-die head, such that the wavelength of the white light emitted from the light diffusion plate can be narrower to achieve the effect of wider color gamut display.

Abstract: A nucleic acid extracting device includes a reagent containing unit, a mixing unit, and a flow channel unit. The reagent containing unit contains a specimen, a magnetic bead, and a reagent for extracting. The mixing unit includes a mixing chamber and a stirring assembly. The mixing chamber includes a chamber portion and a tube portion. The stirring assembly includes a main body and an extension. The main body is provided in the chamber portion. The tube portion connects the chamber portion. And the extension connects the main body and extends into the tube portion. The extension and an inner wall of the tube portion have first and second gaps therebetween respectively along first and second directions of the tube portion. The first gap is less than the second gap. The flow channel unit is connected between the reagent containing unit and the mixing unit.

Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.

Abstract: A device, an instrument and a belt for tying the cervix are provided. The device includes the belt and the instrument. The belt is used to tie the cervix. The instrument includes a first outer pipe, a second outer pipe and two fork structures. The first outer pipe and the second outer pipe are rotatable to each other. The two fork structures are connected individually to corresponding axial ends of the first outer pipe and the second outer pipe, respectively, and insert into the belt detachably.

Abstract: A dynamic flip flop is provided. The dynamic flip-flop comprises a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor. The pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter serving as a tri-state inverter. Therefore, the dynamic flip-flop can be such that makes a master latch to use the tri-state inverter for capturing data in order to reduce electric leakage. In addition, the dynamic flip-flop can also be such that makes a slave latch to use the weak keeper circuit for storing data, thereby avoiding floating point to drive the output.

Abstract: An embodiment of the invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock buffer circuit is used to receive a first clock signal received from the clock input pin and provide a second clock signal and a third clock signal according to the first clock signal. Each of the plurality of flip-flops is used to receive the second clock signal and the third clock signal and store data according to the second clock signal and the third clock signal. Therefore, the multi-bit flip-flop is designed such that makes each of the plurality of flip-flops to share the same clock.

Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.

Abstract: An embodiment of the invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock buffer circuit is used to receive a first clock signal received from the clock input pin and provide a second clock signal and a third clock signal according to the first clock signal. Each of the plurality of flip-flops is used to receive the second clock signal and the third clock signal and store data according to the second clock signal and the third clock signal. Therefore, the multi-bit flip-flop is designed such that makes each of the plurality of flip-flops to share the same clock.

Abstract: A dynamic flip flop is provided. The dynamic flip-flop comprises a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor. The pull-up transistor and the pull-down transistor constitute a feedback inverter, and the feedback inverter is configured as a weak keeper circuit compared to the first inverter serving as a tri-state inverter. Therefore, the dynamic flip-flop can be such that makes a master latch to use the tri-state inverter for capturing data in order to reduce electric leakage. In addition, the dynamic flip-flop can also be such that makes a slave latch to use the weak keeper circuit for storing data, thereby avoiding floating point to drive the output.

Abstract: A device, an instrument and a belt for tying the cervix are provided. The device includes the belt and the instrument. The belt is used to tie the cervix. The instrument includes a first outer pipe, a second outer pipe and two fork structures. The first outer pipe and the second outer pipe are rotatable to each other. The two fork structures are connected individually to corresponding axial ends of the first outer pipe and the second outer pipe, respectively, and insert into the belt detachably.

Abstract: A compressor, an adder circuit, and an operation method thereof are provided. The compressor includes a first adder circuit and a second adder circuit. The first adder circuit receives a plurality of input values. The first adder circuit outputs a first inverted sum value (an inverted signal of a sum value) and a first inverted carry value (an inverted signal of a carry value). One of a plurality of input terminals of the second adder circuit is coupled to the first adder circuit to receive one of the first inverted sum value and the first inverted carry value. The second adder circuit outputs a second inverted sum value and a second inverted carry value.

Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.

Abstract: A post processing apparatus includes a super-resolution (SR) filtering circuit and a loop restoration (LR) filtering circuit. The SR filtering circuit applies SR filtering to a processing result of a preceding circuit. The LR filtering circuit applies LR filtering to a processing result of the SR filtering circuit. Before the SR filtering circuit finishes SR filtering of all pixels of a frame that are generated by the preceding circuit, the LR filtering circuit starts LR filtering of pixels that are derived from applying SR filtering to pixels included in the frame.

Abstract: An integrated circuitry includes a first circuit, a second circuit, and a voltage conversion circuit. A first power supply positive terminal of the first circuit is electrically coupled to a power source. The second circuit is electrically coupled in series with the first circuit and the power source. A second power supply positive terminal of the second circuit is electrically coupled to a first power supply negative terminal of the first circuit. The voltage conversion circuit is electrically coupled between the first circuit and the second circuit so as to receive a signal from the first circuit or the second circuit. The voltage conversion circuit converts a voltage value of the signal according to a first low potential signal of the first power supply negative terminal and a second low potential signal of a second power supply negative terminal.

Abstract: A data latch circuit and a pulse signal generator thereof are provided. The pulse signal generator includes a first buffer, a second buffer, a pull-up switch and an output buffer. The first buffer generates a first buffering signal according to an input signal and a feedback signal. The second buffer generates a second buffering signal according to the input signal and the first buffering signal. The pull-up switch pulls up the second buffering signal according to the first buffering signal. The output buffer generates at least one output pulse signal according to the second buffering signal. The output buffer further outputs the at least one output pulse signal to the first buffer to be the feedback signal.

Abstract: A device, an instrument and a belt for tying the cervix are provided. The device includes the belt and the instrument. The belt is used to tie the cervix. The instrument includes a first outer pipe, a second outer pipe and two fork structures. The first outer pipe and the second outer pipe are rotatable to each other. The two fork structures are connected individually to corresponding axial ends of the first outer pipe and the second outer pipe, respectively, and insert into the belt detachably.

Abstract: Aspects of the disclosure provide a method and device for storing an input image into a memory. The disclosure describes allocating one or more frame buffers in the memory. The disclosure further describes dividing the input image into access units corresponding to subsets of the input image and allocating a main portion and a secondary portion in the frame buffer for each of the access units, wherein at least one of the secondary portions is not sequentially located after its respective main portion within the frame buffer. The disclosure also describes compressing the access units into compressed access units and storing each of the compressed access units into its respective main portion, and if a size of the compressed access unit exceeds a size of the main portion, then storing a remainder of the compressed access unit into its respective secondary portion.

Abstract: Apparatus for immunoassay includes: a cartridge, including at least one test unit; a pin-film assembly, having a second sealing film, a plurality of pierce mechanisms, and a first actuation unit; a plurality of magnetic particles; at least one first magnetic unit; and at least one second magnetic unit. The test unit includes a plurality of fluid chambers, a plurality of pin chambers, a microchannel structure, a buffer chamber, a detection chamber and a waste chamber. The first actuation unit drives the pierce mechanisms to enable a working fluid to flow into the detection chamber storing the magnetic particles. As the second magnetic unit has a magnetic force larger than that of the first magnetic unit and can move reciprocatingly between a third position and a fourth position, the magnetic particles are driven to move reciprocatingly inside the detection chamber, thereby fully mixing the magnetic particles with the working fluid.