Patents by Inventor Chih-Yang Chang

Chih-Yang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210081341
    Abstract: An integrated circuit includes a specific pin, an output circuit, a voltage detector, and a controller. The output circuit is coupled to the specific pin. The voltage detector obtains a detection voltage value from the specific pin. In response to an alert request, the controller provides a control signal to the output circuit based on the detection voltage value, so as to selectively control the output circuit to transmit the alert signal to the specific pin. When the control signal instructs the integrated circuit to operate in a blocking mode, the output circuit blocks the alert signal from being transmitted to the specific pin. When the control signal instructs the integrated circuit to operate in a transmission mode, the output circuit transmits the alert signal to the specific pin.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 18, 2021
    Inventors: Kang-Fu CHIU, Chih-Hung HUANG, Chun-Wei CHIU, Hao-Yang CHANG
  • Patent number: 10946597
    Abstract: The present disclosure provides a measurement method for a molding system comprising an upper mold and a lower mold forming a mold cavity. The method includes applying a pressure difference to a molding resin for driving the molding resin to flow into a preform in the mold cavity; detecting a flow front of the molding resin at a first position and a second position in the mold cavity; and calculating a flowing property of the molding resin based on the first position, the second position, a travelling time of the flow front from the first position to the second position, and the pressure difference.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: March 16, 2021
    Assignees: Coretech System Co., Ltd., National Tsing Hua University
    Inventors: Yuan Yao, Tzu-Heng Chiu, Rong-Yeu Chang, Chia-Hsiang Hsu, Chih-Wei Wang, Shih-Po Sun, Sung-Wei Huang, Hsun Yang, Tsai-Heng Tsai
  • Publication number: 20210068296
    Abstract: An electronic module (EM) carrier includes a sliding bracket coupled to the EM carrier and a handle coupled to the sliding bracket. The handle and sliding bracket are configured to engage with a stationary chassis to hold the EM carrier at a first position in a bay of the stationary chassis when the handle is open. The sliding bracket is further configured to translate the EM carrier to a second position in the stationary chassis when the handle is moved from an open position towards a closed position. In the second position, an EM carrier connector of the EM carrier is engaged with a sled connector of a sled and, in the first position, the EM carrier connector is disengaged from the sled connector.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: TE-MING LIAO, CHUN-YANG TSENG, CHIH-HSIEN CHANG, HSIANG-YIN HUNG, RAYMOND D. HEISTAND, II
  • Patent number: 10936524
    Abstract: A bus system is provided. The bus system includes a master device, a bus, and a plurality of slave devices electrically connected to the master device via the bus. Each slave device has an alert handshake pin. The alert handshake pins of the slave devices are electrically connected together via an alert-handshake control line. When a first slave device communicates with the master device through the bus, in a first phase of a plurality of phases in each assignment period, the first slave device sets the alert-handshake control line to a first voltage level via the alert handshake pin, wherein the first phase corresponds to the first slave device. In the phases other than the first phase in each assignment period, the alert-handshake control line is at a second voltage level. Each of the phases includes two clock cycles.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 2, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Chih-Hung Huang, Chun-Wei Chiu, Hao-Yang Chang
  • Patent number: 10939573
    Abstract: An electronic module (EM) carrier includes a sliding bracket coupled to the EM carrier and a handle coupled to the sliding bracket. The handle and sliding bracket are configured to engage with a stationary chassis to hold the EM carrier at a first position in a bay of the stationary chassis when the handle is open. The sliding bracket is further configured to translate the EM carrier to a second position in the stationary chassis when the handle is moved from an open position towards a closed position. In the second position, an EM carrier connector of the EM carrier is engaged with a sled connector of a sled and, in the first position, the EM carrier connector is disengaged from the sled connector.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Dell Products, L.P.
    Inventors: Te-Ming Liao, Chun-Yang Tseng, Chih-Hsien Chang, Hsiang-Yin Hung, Raymond D. Heistand, II
  • Publication number: 20210055647
    Abstract: A method for fabricating a photomask is provided. The method includes several operations. A photomask substrate, having a chip region and a peripheral region adjacent to the chip region, is received. A reference pattern is formed by emitting one first radiation shot and a first beta pattern is formed by emitting a plurality of second radiation shots in the peripheral region. The plurality of second radiation shots are emitted along a first direction. A roughness of a boundary of the first beta pattern along the first direction is compared to a roughness of a boundary of the reference pattern along the first direction from a top view perspective. An alignment of the plurality of second radiation shots is adjusted if a result of the comparison exceeds a tolerance, or the photomask is formed. A photomask structure thereof and a method for manufacturing a semiconductor are also provided.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: CHENG-MING LIN, HAO-MING CHANG, CHIH-MING CHEN, CHUNG-YANG HUANG
  • Patent number: 10913069
    Abstract: An apparatus for amplifying a nucleic acid sequence in a polymerase chain reaction (PCR) is provided. The apparatus comprises a microprocessor configured to communicatively couple with a user input device and receive instructions from the user input device and implement the received instructions; an electromagnetic radiation (EMR) generator configured to generated EMR at frequencies ranging from 300 THz to 400 THz and communicatively coupled with the microprocessor; a reaction vessel, communicatively coupled with the microprocessor, to house the nucleic acid sequence, necessary reagents to the PCR, and particles comprising a transition metal material, and to receive the EMR generated by the EMR generator; and a temperature sensor communicatively coupled with the reaction vessel and the microprocessor.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 9, 2021
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Dar-Bin Shieh, Chih-Chia Huang, Chen-Min Chang, Tsung-Ju Li, Po-Yang Chang, Ming-Chi Hsieh
  • Publication number: 20210031341
    Abstract: This invention provides an electric screwdriver with an integrated torque adjustment and sensing function, comprising a torque sensor connected between an electric motor and a torque adjuster. The torque sensor comprises a transmission shaft connected to the motor shaft by the shaft, a torque sensing component and at least one planetary gear set. The planetary gear set has a torque output component. The transmission shaft transmits the speed reduced rotational force through the torque output component to drive the output shaft to output a target torque which can be adjusted by the adjuster. The torque sensing component senses the operating torque between the transmission shaft and the torque output component of the torque sensor, thereby assembling to improve the problem that the conventional electric screwdriver can only adjust but cannot accurately sense the operating torque.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 4, 2021
    Inventors: YUN-LUN CHANG, CHIH-CHENG CHOU, YUEH-YANG HU
  • Patent number: 10903274
    Abstract: The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.
    Type: Grant
    Filed: September 22, 2019
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20200411385
    Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a sidewall substantially orthogonal to the first surface and the second surface; and a metallic layer surrounding and connected with the sidewall of the substrate, wherein the metallic layer includes an exposed surface substantially level with the first or second surface of the substrate. Further, a method of manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: September 12, 2020
    Publication date: December 31, 2020
    Inventors: CHI-YANG YU, CHIEN-KUO CHANG, CHIH-HAO LIN, JUNG TSUNG CHENG, KUAN-LIN HO
  • Patent number: 10879306
    Abstract: A micro semiconductor structure is provided. The micro semiconductor structure includes a substrate, a plurality of micro semiconductor devices disposed on the substrate, and a first supporting layer disposed between the substrate and the micro semiconductor devices. Each of the micro semiconductor devices has a first electrode and a second electrode disposed on a lower surface of the micro semiconductor devices. The lower surface includes a region, wherein the region is between the first electrode and the second electrode. An orthographic projection of the first supporting layer on the substrate at least overlaps an orthographic projection of a portion of the region on the substrate. The first supporting layer directly contacts the region.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 29, 2020
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Chih-Ling Wu, Ying-Tsang Liu, Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Yu-Chu Li, Huan-Pu Chang, Yu-Yun Lo, Yi-Min Su, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 10877089
    Abstract: In some embodiments, a semiconductor wafer testing system is provided. The semiconductor wafer testing system includes a semiconductor wafer prober having one or more conductive probes, where the semiconductor wafer prober is configured to position the one or more conductive probes on an integrated chip (IC) that is disposed on a semiconductor wafer. The semiconductor wafer testing system also includes a ferromagnetic wafer chuck, where the ferromagnetic wafer chuck is configured to hold the semiconductor wafer while the wafer prober positions the one or more conductive probes on the IC. An upper magnet is disposed over the ferromagnetic wafer chuck, where the upper magnet is configured to generate an external magnetic field between the upper magnet and the ferromagnetic wafer chuck, and where the ferromagnetic wafer chuck amplifies the external magnetic field such that the external magnetic field passes through the IC with an amplified magnetic field strength.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Harry-Hak-Lay Chuang, Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang
  • Patent number: 10868250
    Abstract: A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10862029
    Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Kuo-Chi Tu, Chih-Yang Chang, Chin-Chieh Yang, Yu-Wen Liao, Wen-Chun You, Sheng-Hung Shih
  • Publication number: 20200381622
    Abstract: A memory cell and method including a first electrode formed through a first opening in a first dielectric layer, a resistive layer formed on the first electrode, a spacing layer formed on the resistive layer, a second electrode formed on the resistive layer, and a second dielectric layer formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening.
    Type: Application
    Filed: August 14, 2020
    Publication date: December 3, 2020
    Inventors: Chih-Yang Chang, Hsia-Wei Chen, Chin-Chieh Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20200365720
    Abstract: A method includes providing a substrate having a gate structure over a first side of the substrate, forming a recess adjacent to the gate structure, and forming in the recess a first semiconductor layer having a dopant, the first semiconductor layer being non-conformal, the first semiconductor layer lining the recess and extending from a bottom of the recess to a top of the recess. The method further includes forming a second semiconductor layer having the dopant in the recess and over the first semiconductor layer, a second concentration of the dopant in the second semiconductor layer being higher than a first concentration of the dopant in the first semiconductor layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chih-Yu Ma, Zheng-Yang Pan, Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Patent number: 10837993
    Abstract: A circuit for measuring a bandwidth of an amplifier includes first and second capacitors, first through third switches, and a pulse generator. First terminals of the capacitors are coupled to an amplifier input, and a second terminal of the second capacitor is coupled to an amplifier output. The first switch has a control terminal and terminals coupled to a first input node and a second terminal of the first capacitor. The second switch has a control terminal and terminals coupled to the amplifier input and output. The third switch has a control terminal, a first terminal, and a second terminal coupled to the second terminal of the first capacitor. The pulse generator has a first output coupled to the control terminal of the third switch, and is configured to vary a pulse width of a pulse signal supplied from the first output to the control terminal of the third switch.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Chow Peng, Chih-Chiang Chang, Wen-Shen Chou, Brady Yang
  • Publication number: 20200357981
    Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Sheng-Hung Shih, Tung-Sheng Hsiao, Wen-Ting Chu, Yu-Wen Liao, I-Ching Chen
  • Publication number: 20200350368
    Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Yang Chang, Wen-Ting Chu
  • Publication number: 20200350369
    Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Inventors: Chih-Yang Chang, Wen-Ting Chu