Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: Methods and apparatus for scanning a code on or in a transparent part, the method comprising: illuminating the code to generate a projected image of the code on a projection surface spaced from the transparent part; and machine scanning the projected image.

Abstract: Methods and apparatus provide in-situ pressure sensors for apparatus used in semiconductor manufacturing processes. In some embodiments, the apparatus may comprise a showerhead body, a first gas channel of the showerhead body, a second gas channel of the showerhead body, one or more first gas pressure sensors positioned on a surface of the first gas channel, and one or more second gas pressure sensors positioned on a surface of the second gas channel. The apparatus may be formed by additive manufacturing including the pressure sensors and electrical connections to the pressure sensors. In some embodiments, a controller may be utilized to control semiconductor processes based on the pressure readings from the in-situ pressure sensors.

Abstract: Methods for texturing a surface of a component which include partially submerging the component within a liquid such that a first portion of the component is not submerged in the liquid and a second portion of the component is submerged in the liquid; and contacting at least the first portion of the component with a laser beam at a power and for a period of time sufficient to texture the first portion of the component to a first surface roughness, wherein the second portion of the component is either not textured by the laser beam, or is textured to a lesser degree than the first portion of the component and has a second surface roughness which is less than the first surface roughness.

Abstract: Various embodiments of the present application are directed a memory layout for reduced line loading. In some embodiments, a memory device comprises an array of bit cells, a first conductive line, a second conductive line, and a plurality of conductive bridges. The first and second conductive lines may, for example, be source lines or some other conductive lines. The array of bit cells comprises a plurality of rows and a plurality of columns, and the plurality of columns comprise a first column and a second column. The first conductive line extends along the first column and is electrically coupled to bit cells in the first column. The second conductive line extends along the second column and is electrically coupled to bit cells in the second column. The conductive bridges extend from the first conductive line to the second conductive line and electrically couple the first and second conductive lines together.

Abstract: An apparatus for ion beam etching is provided. An ion extractor separates a plasma source chamber from a process chamber. A gas inlet provides gas to the plasma source chamber. An RF power system provides RF power to the plasma source chamber. A process gas source and cleaning gas mixture source are connected to the gas inlet.

Abstract: Embodiments of methods of fabricating and refurbishing a component having a seal are provided. A method of fabricating a component having a seal includes: depositing a first layer directly onto a sealing surface of a body, wherein the first layer includes a 3D surface pattern; and depositing a second layer onto the first layer, wherein the second layer includes a seal material. A method of refurbishing a component having a seal includes: providing a component including a body and a seal attached to the body; removing at least a portion the seal from a sealing surface of the body to form an exposed portion of the sealing surface; depositing a first layer directly onto the exposed portion of the sealing surface, wherein the first layer includes a 3D surface pattern; and depositing a second layer onto the first layer, wherein the a second layer includes seal material.

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first resistive random access memory (RRAM) element and a second RRAM element over a substrate. A conductive element is arranged below the first RRAM element and the second RRAM element. The conductive element electrically couples the first RRAM element to the second RRAM element. An upper insulating layer continuously extends over the first RRAM element and the second RRAM element. An upper inter-level dielectric (ILD) structure laterally surrounds the first RRAM element and the second RRAM element. The upper insulating layer separates the first RRAM element and the second RRAM element from the upper ILD structure.

Abstract: A method for forming an elastomer gasket in-situ on a part used for substrate processing that is tunable to a cross-section and/or length of a sealing surface such as a gasket groove or planar sealing surface. The method may include forming, in-situ, a first layer of at least one type of gasket material directly onto a bottom of the sealing surface of the part, forming subsequent layers of the at least one type of gasket material on at least one previously formed layer, and adjusting a number of subsequent layers of the at least one type of gasket material based on dimensions of the sealing surface.

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Abstract: Embodiments of substrate supports for process chambers are provided herein. In some embodiments, a substrate support for a process chamber includes: a pedestal having a support surface for supporting a substrate, one or more heating elements disposed therein, and a radio frequency (RF) electrode disposed therein; a hollow shaft coupled to a lower surface of the pedestal; and an RF rod extending through the hollow shaft and coupled to the RF electrode, wherein an impedance of the RF rod is less than about 0.2 ohms.

Abstract: A method of determining an operational status of a semiconductor manufacturing assembly uses internal vibrations of an in-situ assembly to detect defects. The method may include initiating a first test vibration in an internal structure of the semiconductor manufacturing assembly while the semiconductor manufacturing assembly is in-situ in a semiconductor processing chamber, receiving a first vibration signal caused by the first test vibration, transforming the first vibration signal into a first frequency domain representation of the first vibration signal, determining the operational status of the semiconductor manufacturing assembly based on the first frequency domain representation, and performing a corrective action for the semiconductor manufacturing assembly in response to the operational status.

Abstract: A bimetallic faceplate for substrate processing is provided including a plate having a plurality of gas distribution holes and formed of a first metal having a first coefficient of thermal expansion, the plate having at least one groove around a center of the plate and spaced from the center of the plate; and a metallic element disposed in the at least one groove and fixed to the plate in the at least one groove, the metallic element having a second coefficient of thermal expansion different from the first coefficient of thermal expansion, the metallic element being symmetrically arranged on or in the plate. A chamber for substrate processing is provided that includes a bimetallic faceplate. Also, a method of making a bimetallic faceplate is provided.

Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect within a first inter-level dielectric (ILD) layer over a substrate. A memory device is disposed over the first interconnect and is surrounded by a second ILD layer. A sidewall spacer is arranged along opposing sides of the memory device and an etch stop layer is arranged on the sidewall spacer. The sidewall spacer and the etch stop layer have upper surfaces that are vertically offset from one another by a non-zero distance. A second interconnect extends from a top of the second ILD layer to an upper surface of the memory device.

Abstract: A sealing member includes a monolithic body including a first portion adjoining a second portion. The first portion forms part of a circle. The second portion includes first and second lobes. Each lobe adjoins the first portion with a concave surface. In one example, each lobe includes a rounded tip, and a convex surface extends from one rounded tip to the other rounded tip.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

Abstract: The present disclosure describes a magnetic memory device. The magnetic memory device includes a magnetic sensing array configured to sense an external magnetic field strength. The magnetic memory device further includes a voltage modulator configured to, in response to the external magnetic field strength being greater than a threshold magnetic field strength, provide a test voltage different from a current write voltage of the magnetic memory device. The magnetic memory device further includes an error check array configured to use the test voltage as a write voltage of the error check array and provide a bit error rate corresponding to the test voltage. The magnetic memory device further includes a control unit configured to adjust, based on the bit error rate being equal to or less than a threshold bit error rate, a write voltage of the magnetic memory device from the current write voltage to the test voltage.