Patents by Inventor Chih-Yen Chen

Chih-Yen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210014536
    Abstract: In one method, the current block is partitioned into multiple final sub-blocks using one or more stages of sub-tree partition comprising ternary tree partition and at least one other-type partition, where ternary partition tree is excluded from the sub-tree partition if a current sub-tree depth associated with a current sub-block is greater than a first threshold and the first threshold is an integer greater than or equal to 1. In another method, if a test condition is satisfied, the current block is encoded or decoded using a current Inter mode selected from a modified group of Inter tools, where the modified group of Inter tools is derived from an initial group of Inter tools by removing one or more first Inter tools from the initial group of Inter tools, replacing one or more second Inter tools with one or more complexity-reduced Inter tools, or both.
    Type: Application
    Filed: March 13, 2019
    Publication date: January 14, 2021
    Inventors: Chun-Chia CHEN, Chia-Ming TSAI, Yu-Chi SU, Chen-Yen LAI, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG, Han HUANG
  • Publication number: 20210013331
    Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer. wherein the first recess is located between the drain structure and the gate structure.
    Type: Application
    Filed: July 12, 2019
    Publication date: January 14, 2021
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Publication number: 20210010901
    Abstract: An automatic mounting and demounting device and system for a motor testing platform, adapted to enable a control host to control automatic mounting and demounting between an axle of a motor under test and an axle of a testing apparatus, includes a mobile platform and a positional information sensing member. The control host controls the mobile platform according to positional information generated by the positional information sensing member, such that a carrier for carrying the motor under test is automatically driven to a corresponding position to thereby effect alignment and connection or separation of the axle of the motor under test and the axle of the testing apparatus. Therefore, preparation for the motor dynamics testing is automatically carried out effectively and correctly, thereby reducing the time and manpower required for testing-related preparation.
    Type: Application
    Filed: June 18, 2020
    Publication date: January 14, 2021
    Inventors: MING-YEN CHEN, JIAN-LIN LEE, SHENG-WEI LIN, CHIH-HSIEN WANG
  • Patent number: 10875961
    Abstract: A polycarbonate diol is provided, including three kinds of repeating diol units, wherein one of the repeating diol units is chosen from an alkoxylated diol monomer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 29, 2020
    Assignee: Dairen Chemical Corporation
    Inventors: Fu-Shen Lin, June-Yen Chou, Hsing-Yun Wang, Chih-Jung Chen, Wei-Lun Hsieh
  • Publication number: 20200395529
    Abstract: An ultrasonic sensing device includes a housing, a piezoelectric assembly, a board and a plurality of fixing members. The housing includes a bottom wall, a top wall and a surrounding side wall connected between the top wall and the bottom wall. The piezoelectric assembly includes an encapsulating body and a piezoelectric sheet, wherein at least a portion of the piezoelectric sheet is enclosed by the encapsulating body and has a sensing surface exposed to the encapsulating body and facing the bottom wall. The board is disposed on the top wall of the housing and has a pressing surface facing the encapsulating body and the top wall. The plurality of fixing members is configured to fix the board to the top wall of the housing to press the board to the encapsulating body of the piezoelectric assembly, thereby pressing the sensing surface of the piezoelectric sheet to the bottom wall.
    Type: Application
    Filed: February 20, 2020
    Publication date: December 17, 2020
    Inventors: Chi-Shen Lee, Yu-Yen Fu, Po-Chun Yeh, Dong-Fu Chen, Chih-Wen Cheng, Chi-Lin Huang, Yu-Ping Yen
  • Patent number: 10865268
    Abstract: A method for preparing a wear-resistant hybrid, includes (A) providing nano-silica with hydroxyl groups on its surface to react with an isocyanate-based silane to form silica with silyl groups; (B) subjecting the silica with silyl groups to a hydrolytic condensation reaction by using a sol-gel technology to form highly bifurcated Si-HB nanoparticles with hydroxyl groups; (C) providing a diisocyanate to react with a polyol to form a urethane pre-polymer; and (D) subjecting the Si-HB nanoparticles with hydroxyl groups to an addition reaction with the urethane pre-polymer and with a chain-extending reagent to form a hybrid of Si-polyurethane (PU/Si-HB), whereby a wear-resistant hybrid of Si-polyurethane is prepared.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Chang-Lun Lee, Bei-Huw Shen, Chih-Chia Chen, Wen-Yen Hsieh, Chin-Lung Chiang
  • Publication number: 20200381544
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventor: Chih-Yen CHEN
  • Publication number: 20200377642
    Abstract: A method for preparing a wear-resistant hybrid, includes (A) providing nano-silica with hydroxyl groups on its surface to react with an isocyanate-based silane to form silica with silyl groups; (B) subjecting the silica with silyl groups to a hydrolytic condensation reaction by using a sol-gel technology to form highly bifurcated Si-HB nanoparticles with hydroxyl groups; (C) providing a diisocyanate to react with a polyol to form a urethane pre-polymer; and (D) subjecting the Si-HB nanoparticles with hydroxyl groups to an addition reaction with the urethane pre-polymer and with a chain-extending reagent to form a hybrid of Si-polyurethane (PU/Si-HB), whereby a wear-resistant hybrid of Si-polyurethane is prepared.
    Type: Application
    Filed: October 14, 2019
    Publication date: December 3, 2020
    Inventors: Chang-Lun Lee, Bei-Huw Shen, Chih-Chia Chen, Wen-Yen Hsieh, Chin-Lung Chiang
  • Publication number: 20200379335
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 10840131
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Publication number: 20200353721
    Abstract: An electronic device is provided. The electronic device includes a display, a substrate, and an anti-explosion layer. The substrate is disposed on the display. The anti-explosion layer is disposed between the substrate and the display, and the anti-explosion layer has a tensile strength in a range from 10 MPa to 30 MPa.
    Type: Application
    Filed: April 17, 2020
    Publication date: November 12, 2020
    Inventors: Chao-Li CHUANG, Hsin-Wei HUANG, Ming-Chi GUO, Chih-Yen LU, Kuan-Chou CHEN
  • Patent number: 10831094
    Abstract: The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 10, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20200350317
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20200335616
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.
    Type: Application
    Filed: April 17, 2019
    Publication date: October 22, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Chang-Xiang Hung
  • Patent number: 10804385
    Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: October 13, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Publication number: 20200321442
    Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.
    Type: Application
    Filed: June 21, 2020
    Publication date: October 8, 2020
    Inventors: Yi-Fan Li, Wen-Yen Huang, Shih-Min Chou, Zhen Wu, Nien-Ting Ho, Chih-Chiang Wu, Ti-Bin Chen
  • Patent number: 10773274
    Abstract: A miniature fluid control device is provided and includes a gas inlet plate, a resonance plate and a piezoelectric actuator. The resonance plate is assembled and combined with the gas inlet plate. The piezoelectric actuator is assembled and combined with the resonance plate. The piezoelectric actuator includes a suspension plate, an outer frame, at least one bracket and a piezoelectric plate. The suspension plate has a first surface and a second surface. The outer frame is arranged around the suspension plate and has an assembling surface. The piezoelectric plate is attached on the second surface. The at least one bracket is formed between the suspension plate and the outer frame as making the first surface of the suspension plate non-coplanar with the assembling surface of the outer frame, so that a specific chamber spacing is maintained between the first surface of the suspension plate and the resonance plate.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: September 15, 2020
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ying-Lun Chang, Shih-Chang Chen, Chih-Feng Lin, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai
  • Patent number: 10777076
    Abstract: A license plate recognition system and a license plate recognition method are provided. The license plate recognition system includes an image capturing module, a determination module and an output module. The image capturing module is utilized for capturing an image of a target object. The determination module is utilized for dividing the image of the target object into a plurality of image blocks. The determination module utilizes the plurality of image blocks to generate feature data and perform a data sorting process on the feature data to generate a first sorting result. The output module outputs the sorting result.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 15, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Shu-Heng Chen, Chih-Lun Liao, Cheng-Feng Shen, Li-Yen Kuo, Yu-Shuo Liu, Shyh-Jian Tang, Chia-Lung Yeh
  • Patent number: 10770345
    Abstract: A method for fabricating an integrated circuit is provided. The method includes depositing a first polish stop layer above a memory device, in which the first polish stop layer has a first portion over the memory device and a second portion that is not over the memory device; removing the second portion of the first polish stop layer; depositing an inter-layer dielectric layer over the first polish stop layer after removing the second portion of the first polish stop layer; and polishing the inter-layer dielectric layer until reaching the first portion of the first polish stop layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chang-Sheng Lin, Chien-Chung Huang, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Chih-Yuan Ting, Jyu-Horng Shieh
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng