Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a compound semiconductor layer disposed over the barrier layer, a gate electrode disposed over the compound semiconductor layer, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. The source electrode and the drain electrode penetrate through at least a portion of the barrier layer. The semiconductor device also includes a source field plate connected to the source electrode through a source contact. The semiconductor device further includes a first electric field redistribution pattern disposed on the barrier layer and directly under the edge of the source field plate.

Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer. wherein the first recess is located between the drain structure and the gate structure.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a channel layer disposed on a substrate, a barrier layer disposed on the channel layer, and a nitride layer disposed on the barrier layer. The semiconductor device also includes a compound semiconductor layer that includes an upper portion and a lower portion, wherein the lower portion penetrates through the nitride layer and a portion of the barrier layer. The semiconductor device also includes a spacer layer conformally disposed on a portion of the barrier layer and extending onto the nitride layer. The semiconductor device further includes a gate electrode disposed on the compound semiconductor layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extends through the spacer layer, the nitride layer, and at least a portion of the barrier layer.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.

Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a source/drain pair, a fluorinated region, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer is disposed over the barrier layer. The source/drain pair is disposed over the substrate, wherein the source and the drain are located on opposite sides of the compound semiconductor layer. The fluorinated region is disposed in the compound semiconductor layer. The gate is disposed on the compound semiconductor layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a dopant holding layer, a source/drain pair, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer and the dopant holding layer are disposed over the barrier layer. The source/drain pair are disposed over the substrate and on both sides of the compound semiconductor layer. The gate is disposed over the compound semiconductor layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a dopant holding layer, a source/drain pair, and a gate. The channel layer is disposed over the substrate. The barrier layer is disposed over the channel layer. The compound semiconductor layer and the dopant holding layer are disposed over the barrier layer. The source/drain pair are disposed over the substrate and on both sides of the compound semiconductor layer. The gate is disposed over the compound semiconductor layer.

Abstract: A semiconductor device includes a channel layer, a first barrier layer, a second barrier layer, a source electrode, a drain electrode and a gate structure. The channel layer, the first barrier layer, and the second barrier layer are sequentially stacked over a substrate. The source electrode, a drain electrode and the gate structure extend through at least portions of the second barrier layer. The source electrode, the drain electrode and the gate structure have respective bottom surfaces located at substantially the same level as and adjacent to the first barrier layer.

Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.

Abstract: A high electron mobility transistor includes a III-V compound layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a surface plasma treatment region, and at least one moat. The nitride layer is disposed on the III-V compound layer. The source and the drain electrodes are disposed above the III-V compound layer. The gate electrode is disposed above the nitride layer. The moat is at least partially disposed in the nitride layer and between the source and the drain electrodes. The surface plasma treatment region is at least partially disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer between the moat and the drain electrode, a top surface of the nitride layer between the moat and the source electrode, and/or a top surface of the nitride layer under the moat.

Abstract: A nitride semiconductor device is disclosed. A substrate is provided. A nitride semiconductor layer is disposed on the substrate. An AlN anode dielectric layer is disposed on the nitride semiconductor layer. An anode metal layer is disposed on the AlN anode dielectric layer. A fluorinated region is disposed in the AlN anode dielectric layer. The fluorinated region extends into the nitride semiconductor layer.

Abstract: A thermal control apparatus is provided. The thermal control apparatus includes a controller and a thermoelectric cooling module. The thermoelectric cooling module includes: a thermal sensor for measuring a first current temperature of a first location of the thermoelectric cooling module; and a thermoelectric cooling device for adjusting the first current temperature according to a control signal from the controller. The controller calculates a predicted temperature of a second location of the thermoelectric cooling module according to the measured first current temperature and a thermal model between the first location and the second location. The controller further automatically adjusts a first target temperature of the first location according to the predicted temperature and an expected temperature of the second location, and controls the thermoelectric cooling device to automatically adjust the first current temperature of the first location to reach the first target temperature.

Abstract: A high electron mobility transistor includes a channel layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a fluorinated region, and a surface plasma treatment region. The nitride layer is disposed on the channel layer. The source electrode and the drain electrode are disposed above the channel layer. The gate electrode is disposed above the nitride layer and at least partially disposed between the source electrode and the drain electrode in a first direction. The fluorinated region is disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer located between the source electrode and the drain electrode. The surface plasma treatment region is separated from the fluorinated region or a fluorine concentration of the surface plasma treatment region is different from a fluorine concentration of the fluorinated region.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, and a first anti-polarization layer. The barrier layer is disposed above the channel layer. The first anti-polarization layer is disposed under the channel layer. A thickness of the first anti-polarization layer is substantially equal to a thickness of the barrier layer. An atomic ratio of a group III element in the first anti-polarization layer is substantially equal to an atomic ratio of the group III element in the barrier layer.

Abstract: A high electron mobility transistor includes a III-V compound layer, a nitride layer, a source electrode, a drain electrode, a gate electrode, a surface plasma treatment region, and at least one moat. The nitride layer is disposed on the III-V compound layer. The source and the drain electrodes are disposed above the III-V compound layer. The gate electrode is disposed above the nitride layer. The moat is at least partially disposed in the nitride layer and between the source and the drain electrodes. The surface plasma treatment region is at least partially disposed in the nitride layer. The surface plasma treatment region is at least partially disposed at a top surface of the nitride layer between the moat and the drain electrode, a top surface of the nitride layer between the moat and the source electrode, and/or a top surface of the nitride layer under the moat.

Abstract: A high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer, a source electrode, a drain electrode, a gate electrode, a first moat, and a second moat. The second III-V compound layer is disposed on the first III-V compound layer. The source electrode and the drain electrodes are disposed above the first III-V compound layer. The gate electrode is disposed above the second III-V compound layer located between the source and the drain electrodes in a first direction. The second III-V compound layer includes a first region under the gate electrode. The first moat is at least partially disposed between the first region and the source electrode in the first direction. The second moat is at least partially disposed between the first region and the drain electrode in the first direction.

Abstract: A light guide module includes a light guide plate and a gradient index lens. The light guide plate has a light output surface and a light incident surface. The light incident surface is connected to the light output surface. The gradient index lens has a first surface, a second surface and a third surface. The first surface and the second surface are connected to the third surface. The first surface of the gradient index lens is attached to the light output surface. Multiple internal refractive indexes of the gradient index lens are increased gradually from the first surface to the second surface. A minimum refractive index of the multiple internal refractive indexes is less than a refractive index of the light guide plate. The incident light is refracted multiple times within the gradient index lens, and totally reflected back to the light guide plate.

Abstract: A light guide module includes a light guide plate and a gradient index lens. The light guide plate has a light output surface and a light incident surface. The light incident surface is connected to the light output surface. The gradient index lens has a first surface, a second surface and a third surface. The first surface and the second surface are connected to the third surface. The first surface of the gradient index lens is attached to the light output surface. Multiple internal refractive indexes of the gradient index lens are increased gradually from the first surface to the second surface. A minimum refractive index of the multiple internal refractive indexes is less than a refractive index of the light guide plate. The incident light is refracted multiple times within the gradient index lens, and totally reflected back to the light guide plate.