Patents by Inventor Chih-Yi Chen

Chih-Yi Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107207
    Abstract: A semiconductor structure includes a semiconductor substrate; fin active regions protruded above the semiconductor substrate; and a gate stack disposed on the fin active regions; wherein the gate stack includes a high-k dielectric material layer, and various metal layers disposed on the high-k dielectric material layer. The gate stack has an uneven profile in a sectional view with a first dimension D1 at a top surface, a second dimension D2 at a bottom surface, and a third dimension D3 at a location between the top surface and the bottom surface, and wherein each of D1 and D2 is greater than D3.
    Type: Application
    Filed: December 9, 2024
    Publication date: March 27, 2025
    Inventors: Chi-Sheng LAI, Wei-Chung SUN, Yu-Bey WU, Yuan-Ching PENG, Yu-Shan LU, Li-Ting CHEN, Shih-Yao LIN, Yu-Fan PENG, Kuei-Yu KAO, Chih-Han LIN, Jing Yi YAN, Pei-Yi LIU
  • Publication number: 20250105163
    Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.
    Type: Application
    Filed: March 20, 2024
    Publication date: March 27, 2025
    Inventors: Liang-Kai CHEN, Chih-Chiang HUNG, Wen-Yi JIAN, Yuan-Hung LIN, Sheng-Fan YANG
  • Patent number: 12260669
    Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: March 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Yu-Feng Chen, Chung-Shi Liu, Chen-Hua Yu, Hao-Yi Tsai, Yu-Chih Huang
  • Patent number: 12255196
    Abstract: Manufacturing method of semiconductor package includes following steps. Bottom package is provided. The bottom package includes a die and a redistribution structure electrically connected to die. A first top package and a second top package are disposed on a surface of the redistribution structure further away from the die. An underfill is formed into the space between the first and second top packages and between the first and second top packages and the bottom package. The underfill covers at least a side surface of the first top package and a side surface of the second top package. A hole is opened in the underfill within an area overlapping with the die between the side surface of the first top package and the side surface of the second top package. A thermally conductive block is formed in the hole by filling the hole with a thermally conductive material.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20250087888
    Abstract: An antenna assembly includes a patch antenna, a metal layer, and a feed-in signal layer. The metal layer is disposed on a side of the patch antenna and includes a first slot and a second slot. The feed-in signal layer is disposed on a side of the metal layer opposite the second antenna and includes a transmitting port, a receiving port, a hybrid coupler, and two microstrips. The transmitting port and the receiving port are connected to the hybrid coupler, and the two microstrips are extended in the direction away from the hybrid coupler. Projections of two ends of the two microstrips onto the metal layer are overlapped with the first slot and the second slot. An antenna array is also mentioned.
    Type: Application
    Filed: May 30, 2024
    Publication date: March 13, 2025
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Hsin-Feng Hsieh, Wu-Hua Chen, Chih-Wei Liao, Chao-Hsu Wu
  • Publication number: 20250089364
    Abstract: A integrated circuit includes a first, a second, a third, and a fourth gate, a first input pin and a first conductor. The first and third gate are on a first level. The second and fourth gate are on a second level. The second gate is coupled to the first gate. The fourth gate is coupled to the third gate. The first input pin extends in a second direction, is on a first metal layer above a front-side of a substrate, is coupled to the first gate, and configured to receive a first input signal. The first input pin is electrically coupled to the third gate by the first, second or fourth gate. The first conductor extends in the first direction, is on a second metal layer below a back-side of the substrate, and is coupled to the second and fourth gate.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Inventors: Cheng-Ling WU, Chih-Liang CHEN, Chi-Yu LU, Yi-Yi CHEN, Ting-Yun WU
  • Publication number: 20250079414
    Abstract: An electronic package module and a method for fabrication of the same are provided. The method includes providing an electronic component assembly and a circuit substrate. The electronic component assembly includes two electronic components and a conductive structure. The electronic components are connected to each other through a conductive adhesive material, while the electronic components are connected to the conductive structure through another conductive adhesive material. A soldering material is formed on the circuit substrate, and the electronic component assembly is disposed on the soldering material. The melting points of the conductive adhesive materials are higher than the melting point of the soldering material. As a result, the conductive adhesive materials are prevented from failure during the soldering process, and thus the process yield is improved.
    Type: Application
    Filed: January 16, 2024
    Publication date: March 6, 2025
    Inventors: KUO-HSIEN LIAO, LI-CHENG SHEN, HUNG-YI TSAI, CHAO-HSUAN WANG, CHUN-MING CHEN, TAI-LIN WU, CHIH-SHIEN CHEN, PING-CHI HUNG
  • Patent number: 12245521
    Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: March 4, 2025
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Wei Kuo, Chung Yi Chiu, Yi-Wei Tseng, Hsuan-Hsu Chen, Chun-Lung Chen
  • Publication number: 20250072032
    Abstract: A semiconductor power device includes a substrate, a channel layer, a barrier layer, a gate, a source, and a drain. The channel layer is located on the substrate. The barrier layer is located on the channel layer and includes a first region and a second region outside the first region. There is a first compound in the first region and a second compound in the second region. The first compound and the second compound each have an aluminum atom of a different ratio, and the aluminum composition ratio of the first compound is less than the aluminum composition ratio of the second compound. The ratio consists of a plurality of different atoms in the first compound and the second compound.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Shin-Yi Huang, Hua-Mao Chen, Chih-Hung Yen
  • Publication number: 20250072052
    Abstract: A device includes a transistor. The transistor includes a plurality of stacked channels, a source/drain region coupled to the stacked channels, and a gate metal wrapped around the stacked channels. The transistor includes a plurality of inner spacers, each inner spacer being positioned laterally between the gate metal and the source/drain region and including a gap and an inner spacer liner layer between the gate metal and the source/drain region.
    Type: Application
    Filed: January 11, 2024
    Publication date: February 27, 2025
    Inventors: Chun Yi CHOU, Guan-Lin CHEN, Shi Ning JU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250060624
    Abstract: A self-powered display device includes a display module and a power module. The display module is a cholesteric liquid crystal display module, and the power module is a solar cell module. The display module allows light to enter the power module from the front side, and the power module generates electricity upon receiving the light to provide the necessary energy for the display module to show images. The power module has multiple active areas and multiple inactive areas between the active areas. When the width of the inactive area is less than or equal to 50 ?m, the human eye will have difficulty discerning the width of the inactive area. Additionally, a shielding layer can be placed on the inactive area to ensure that the visual color difference (?E) between the inactive area and the active area does not exceed 10 color difference units, thereby improving the image quality.
    Type: Application
    Filed: October 27, 2023
    Publication date: February 20, 2025
    Inventors: CHUNG-YI CHANG, CHIH-WEI CHEN, CHI-CHANG LIAO
  • Patent number: 12224784
    Abstract: A signal adjusting circuit and a receiving end circuit using the same are provided. The signal adjusting circuit is adapted to a peak detector, and includes a first amplifier and a first feedback circuit. The first amplifier receives a first input signal, and amplifies the first input signal to output a first output signal. The first feedback circuit is connected between a first input terminal and a first output terminal of the first amplifier, and is configured to determine a first gain of the first output signal. The peak detector is connected to a first output node of the first feedback circuit, so as to receive a first detection signal and detect a peak value of the first detection signal. The peak detector has a predetermined power input range, and the first feedback circuit keeps the first detection signal within the predetermined power input range.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: February 11, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Sie-Siou Jhang-Jian, Hsuan-Yi Su, Chih-Lung Chen
  • Publication number: 20250038073
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Han SHEN, Chih-Yuan CHEN, Jiung WU, Hung-Yi Kuo, Chung-Ju LEE, Tung-He CHOU, Ji CUI, Kuo-Chung YEE, Chen-Hua YU, Cheng-Chieh HSIEH, Yu-Jen LIEN, Yian-Liang KUO, Shih-Hao TSENG, Jen Yu WANG, Tzu-Chieh Chou
  • Publication number: 20250038070
    Abstract: A device including a first vertical field effect transistor having a first drain/source region and a second drain/source region, and a second vertical field effect transistor having a third drain/source region and a fourth drain/source region. The device including a first power contact situated on a frontside of the device and coupled to the first drain/source region, a second power contact situated on the frontside of the device and coupled to the third drain/source region, and a contact situated on a backside of the device and coupled to the second drain/source region and to the fourth drain/source region.
    Type: Application
    Filed: July 25, 2023
    Publication date: January 30, 2025
    Inventors: Yi-Yi Chen, Chi-Yu Lu, Chih-Liang Chen, LI-CHUN TIEN
  • Patent number: 12194790
    Abstract: A tire pressure detection device includes a chip, a Bluetooth receiving circuit, a Bluetooth antenna, a battery, an LF trigger coil, a power switch, an LF trigger switch and a monitor respectively connected to a case. The Bluetooth receiving circuit is electrically connected to the chip and the Bluetooth antenna. The LF trigger coil, the power switch, the LF trigger switch and the monitor are respectively connected to the chip. A user holds and inserts the tire pressure detection through a double rims. The chip sends an LF signal via the LF trigger coil to activate a Bluetooth tire pressure detector at the inner rim to detect tire pressure. A pressure signal of an inner tire is sent to the chip via the Bluetooth antenna and the Bluetooth receiving circuit. The chip displays the tire pressure of the inner tire on the monitor to be checked by the user.
    Type: Grant
    Filed: November 9, 2022
    Date of Patent: January 14, 2025
    Inventor: Chih-Yi Chen
  • Publication number: 20230072393
    Abstract: A tire pressure detection device includes a chip, a Bluetooth receiving circuit, a Bluetooth antenna, a battery, an LF trigger coil, a power switch, an LF trigger switch and a monitor respectively connected to a case. The Bluetooth receiving circuit is electrically connected to the chip and the Bluetooth antenna. The LF trigger coil, the power switch, the LF trigger switch and the monitor are respectively connected to the chip. A user holds and inserts the tire pressure detection through a double rims. The chip sends an LF signal via the LF trigger coil to activate a Bluetooth tire pressure detector at the inner rim to detect tire pressure. A pressure signal of an inner tire is sent to the chip via the Bluetooth antenna and the Bluetooth receiving circuit. The chip displays the tire pressure of the inner tire on the monitor to be checked by the user.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 9, 2023
    Inventor: Chih-Yi Chen
  • Publication number: 20200384814
    Abstract: A tire pressure detection device includes an emitter and a receiver. The emitter is installed to a tire to detect tire pressure, and the emitter sends the tire pressure data via Bluetooth communication to the receiver. The receiver is operated by a user so as to pair the emitter on the tire that is to be checked. The receiver is an elongate part which includes an LF trigger coil connected to the front end thereof. The LF trigger coil is moved to close to the emitter and activates the emitter, such that the tire pressure is sent to the receiver. The emitter has to be paired with the receiver to send the tire pressure to the receiver.
    Type: Application
    Filed: May 26, 2020
    Publication date: December 10, 2020
    Inventor: Chih-Yi Chen
  • Publication number: 20160308319
    Abstract: A DC power plug, which is adapted for being coupled to an electronic device, an external device, and an external power source, includes a wire, an external plug, and an adaptor. The wire includes a power pin set configured to be coupled to the external power source. The external plug, which is configured to be coupled to the external device, includes a first external pin set coupled to the power pin set and a second external pin set. The adaptor, which is configured to be coupled to the electronic device, includes a first adapting pin set coupled to the power pin set and a second adapting pin set coupled to the second external pin set.
    Type: Application
    Filed: August 27, 2015
    Publication date: October 20, 2016
    Inventors: Yu-Shih WANG, Yang-Kun OU, Wei-Yu CHEN, Chia-Chieh LIU, Chih-Yi CHEN
  • Patent number: 9238620
    Abstract: The invention relates to uses of the sulfur-containing compound in inhibiting activities of a factor related to cancer metastasis and/or growth. Preferably, the invention relates to uses of the sulfur-containing compound in inhibiting lung cancer metastasis and/or growth.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 19, 2016
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Chieh-Hsi Wu, Jyh-Horng Sheu, Chih-Yi Chen, Yi-Chung Chien, Shuo-Chueh Chen, Chun-Hsu Pan, Chiung-Yao Huang
  • Patent number: D1063925
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: February 25, 2025
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Po-Yang Chien, Hao-Jen Fang, Wei-Yi Chang, Chun-Chieh Chen, Chen-Cheng Wang, Chih-Wen Chiang, Sheng-Hung Lee