Patents by Inventor Chih-Yi Huang
Chih-Yi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12147277Abstract: An electronic device including a first body, a second body, a pivoting shaft, a driving module, and a light source is provided. The first body includes a first casing and a second casing movably disposed on the first casing. The second body has a pivoting part and a light reflecting part located at the pivoting part. The pivoting shaft is connected to the pivoting part. The second body is pivoted to the first body through the pivoting shaft. The pivoting shaft, the driving module, and the light source are disposed in the first body. The driving module is connected to the pivoting shaft and contacts the second casing. When the second body rotates relative to the first body, the pivoting shaft drives the driving module to push the second casing to lift to form a light emitting slit between the second casing and the pivoting part.Type: GrantFiled: November 1, 2022Date of Patent: November 19, 2024Assignee: COMPAL ELECTRONICS, INC.Inventors: Che-An Wu, Chuang-Yuan Cheng, Chen-Yi Huang, Hao-Jen Fang, Chih-Wen Chiang
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Publication number: 20240379423Abstract: A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.Type: ApplicationFiled: July 25, 2024Publication date: November 14, 2024Inventors: Chien CHANG, Min-Hsiu HUNG, Yu-Hsiang LIAO, Yu-Shiuan WANG, Tai Min CHANG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20240379670Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.Type: ApplicationFiled: June 6, 2023Publication date: November 14, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
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Patent number: 12142843Abstract: An electronic device, including a metal back cover, a ground radiator, a third radiator, and a metal frame including a first cutting opening, a second cutting opening, a first radiator located between the first cutting opening and the second cutting opening, and a second radiator located beside the second cutting opening and separated from the first radiator by the second cutting opening, is provided. An end of a first slot formed between the metal back cover and a first part of the first radiator is communicated with the first cutting opening, and a second slot formed between the metal back cover and a second part of the first radiator and between the metal back cover and the second radiator is communicated with the second cutting opening. The ground radiator connects the metal back cover and the first radiator and separates the first slot from the second slot.Type: GrantFiled: February 23, 2023Date of Patent: November 12, 2024Assignee: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Chao-Hsu Wu, Hau Yuen Tan, Chih-Wei Liao, Shih-Keng Huang, Wen-Hgin Chuang, Chia-Hong Chen, Lin-Hsu Chiang, Han-Wei Wang, Chun-Jung Hu
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Publication number: 20240363464Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
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Publication number: 20240363676Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The magnetic element has multiple sub-layers, and each sub-layer is wider than another sub-layer above it. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element, and the isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.Type: ApplicationFiled: July 9, 2024Publication date: October 31, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Cheng CHEN, Wei-Li HUANG, Chun-Yi WU, Kuang-Yi WU, Hon-Lin HUANG, Chih-Hung SU, Chin-Yu KU, Chen-Shien CHEN
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Publication number: 20240355741Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.Type: ApplicationFiled: July 1, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
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Patent number: 12112217Abstract: An electronic card receiving device, including a housing, a card stand, a rotating shaft, and a contact element, is provided. The housing includes a front plate having an opening. The card stand is disposed in an inner space of the housing and includes a plate section, a connecting section, and a hook section. The connecting section is connected between the plate section and the hook section. A terminal of the hook section protrudes toward the opening. The rotating shaft is attached to the plate section and is lower than the opening. An axis of the rotating shaft is substantially parallel to the front plate. The rotating shaft rotates to drive the card stand to oscillate between an initial configuration and a card-reading configuration. The contact element is disposed on the plate section of the card stand. A method of using an electronic card receiving device is also provided.Type: GrantFiled: December 7, 2022Date of Patent: October 8, 2024Assignee: E Ink Holdings Inc.Inventors: Huei-Chuan Lee, Bo-Tsang Huang, Chu-Kuang Tseng, Chin-Chi Yu, Chih-Chun Chen, Kai-Yi Cho
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Publication number: 20240328078Abstract: An artificial leather and a method for manufacturing the artificial leather are provided. The artificial leather includes a fabric layer, a thermoplastic polyolefin layer, a modified thermoplastic polyolefin layer, and a polyurethane surface layer. The thermoplastic polyolefin layer is disposed on the fabric layer. The modified thermoplastic polyolefin layer is disposed on the thermoplastic polyolefin layer. The polyurethane surface layer is attached to the modified thermoplastic polyolefin layer through an adhesive.Type: ApplicationFiled: March 20, 2024Publication date: October 3, 2024Inventors: CHIH-YI LIN, Kuo-Kuang Cheng, Chien-Chia Huang, Chi-Chin Chiang, Wen-Hsin Tai, Chieh Lee, Yu-Lun Chen, Yu Hung Liu
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Patent number: 12107548Abstract: An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.Type: GrantFiled: April 13, 2021Date of Patent: October 1, 2024Assignee: RichWave Technology Corp.Inventors: Pin-Yi Huang, Chih-Sheng Chen, Ching-Wen Hsu
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Publication number: 20240319590Abstract: Optical devices and methods of manufacture are presented in which a first mask is utilized for multiple purposes. Some methods include depositing a first mask over a support material, forming a concave surface in the support material through the first mask, and bonding the first mask to a first bonding layer over an optical interposer.Type: ApplicationFiled: March 20, 2023Publication date: September 26, 2024Inventors: Yu-Hung Lin, Yu-Yi Huang, Chih-Hao Yu, Yu-Ting Yen, Shih-Peng Tai
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Publication number: 20240296296Abstract: Embodiments of the present disclosure relate to a method, system, and computer program product for translation of rich text. In some embodiments, a method is disclosed. According to the method, one or more candidate formats are determined for source rich text. A target format for the source rich text is selected from the one or more candidate formats based on one or more corresponding images obtained from rendering the source rich text in the one or more candidate formats. Based on the target format, a translation editing environment is provided for editing a translation of the source rich text. In other embodiments, a system and a computer program product are disclosed.Type: ApplicationFiled: March 2, 2023Publication date: September 5, 2024Inventors: Jin Shi, CHIH-YUAN LIN, Shu-Chih Chen, PEI-YI LIN, Chao Yuan Huang
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Publication number: 20240297163Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.Type: ApplicationFiled: May 12, 2024Publication date: September 5, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
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Patent number: 12080943Abstract: An antenna module disposed on a substrate having a first and a second surface opposite to each other includes a microstrip line, a first radiator, a ground radiator and a ground plane. The microstrip line, the first radiator and the ground radiator are disposed on the first surface. The microstrip line includes a first and a second end opposite to each other. The first end includes a first feeding end. The first radiator is connected to the second end of the microstrip line. The ground radiator surrounds the microstrip line and the first radiator and has a first opening and two opposite grounding ends. The first end of the microstrip line is located in the first opening. A gap is formed between each grounding end and the first feeding end. The ground plane is disposed on the second surface. The ground radiator is connected to the ground plane.Type: GrantFiled: February 22, 2022Date of Patent: September 3, 2024Assignee: PEGATRON CORPORATIONInventors: Chien-Yi Wu, Tse-Hsuan Wang, Chih-Fu Chang, Chao-Hsu Wu, Shih-Keng Huang, Hau Yuen Tan
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Publication number: 20240290734Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hsuan TAI, Ting-Ting KUO, Yu-Chih HUANG, Chih-Wei LIN, Hsiu-Jen LIN, Chih-Hua CHEN, Ming-Da CHENG, Ching-Hua HSIEH, Hao-Yi TSAI, Chung-Shi LIU
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Patent number: 12074193Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.Type: GrantFiled: March 30, 2023Date of Patent: August 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Cheng Chen, Wei-Li Huang, Chun-Yi Wu, Kuang-Yi Wu, Hon-Lin Huang, Chih-Hung Su, Chin-Yu Ku, Chen-Shien Chen
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Publication number: 20240281612Abstract: A method, computer system, and a computer program product for task assistance is provided. The present invention may include acquiring a request expression input by a user. The present invention may include identifying a request intent associated with a task based on the request expression. The present invention may include determining a response script corresponding to the request intent. The present invention may include executing the response script to complete the task and presenting the process of running the task in a user-interface (UI).Type: ApplicationFiled: February 21, 2023Publication date: August 22, 2024Inventors: Jin Shi, CHIH-YUAN LIN, Shu-Chih Chen, Chao Yuan Huang, PEI-YI LIN
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Patent number: 12068212Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, a conductive terminal, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The conductive terminal is connected to the redistribution layer. The through via extends through the encapsulant and the redistribution layer to contact the conductive terminal and the second RDL structure.Type: GrantFiled: April 11, 2022Date of Patent: August 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Hsuan Tai, Chih-Hua Chen, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo
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Patent number: 12067327Abstract: A display apparatus, which is electrically connected to a host, is provided. The display apparatus includes a display panel, a display controller, an audio interface, and an audio-processing chip. The display controller is configured to control displaying of the display panel. The audio interface includes a detection circuit configured to detect whether a pair of headphones is plugged into the audio interface. The audio-processing chip is configured to receive an audio signal from the host, and to convert the audio signal into an output audio signal. When the detection circuit detects that the pair of headphones has been plugged into the audio interface, the audio-processing chip adjusts strength of the output audio signal according to a headphone-volume setting of the display apparatus, and transmits the adjusted output audio signal to the pair of headphones for playback through the audio interface.Type: GrantFiled: May 25, 2022Date of Patent: August 20, 2024Assignee: GIGA-BYTE TECHNOLOGY CO., LTD.Inventors: Cheng-Lung Lin, Tzu-Yi Tsao, Chih-Cheng Huang
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Patent number: 12057397Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.Type: GrantFiled: December 5, 2022Date of Patent: August 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shuen-Shin Liang, Chun-I Tsai, Chih-Wei Chang, Chun-Hsien Huang, Hung-Yi Huang, Keng-Chu Lin, Ken-Yu Chang, Sung-Li Wang, Chia-Hung Chu, Hsu-Kai Chang